Questions: Addressing Modes and Instruction Format

Question 1

A compiler needs to access element A[i] of an integer array, where the array's base address is in R1 and the index i is in R2. Which addressing mode is most appropriate?

• A. Immediate mode — embed the element value directly in the instruction
• B. Direct addressing — use a fixed memory address stored in the instruction
• C. Scaled indexed addressing — compute address as R1 + R2 × element_size at runtime
• D. Register mode — the value is already in a register, no memory access needed

Answer: (C)

Array element access requires computing an address at runtime from a base address plus an index scaled by element size (e.g., R1 + R2 × 4 for 4-byte integers). Scaled indexed addressing does this directly in hardware. Immediate mode only works for compile-time constants embedded in the instruction. Direct addressing uses a fixed address and cannot handle a runtime index. Register mode reads a register value — it does not access memory.

Question 2

Processor A uses fixed 32-bit instructions; Processor B uses variable-length instructions (1–15 bytes). Which statement correctly identifies a tradeoff?

• A. Fixed-length instructions have more complex decode logic but allow richer addressing modes
• B. Variable-length instructions simplify pipeline design but restrict addressing to immediate and register modes
• C. Fixed-length instructions simplify pipeline design (all fetches are identical) but constrain the range of immediate values and addressing modes that fit in a fixed bit budget
• D. Variable-length instructions are always faster because they use fewer total bytes

Answer: (C)

Fixed-length instructions (like ARM's 32-bit format) allow the pipeline to fetch and decode without first determining instruction size — simplifying the fetch/decode stage significantly. The cost is that every instruction must encode opcode, registers, immediate, and addressing mode bits within a fixed budget, limiting expressiveness. Variable-length formats (like x86) can express richer addressing modes and larger immediate values, but require complex decode logic to find instruction boundaries before decoding begins.

Question 3

Register indirect addressing — loading from the address stored in a register rather than from the register's value — is the hardware mechanism that implements pointer dereferencing.

• T. True
• F. False

Answer: True

When a program dereferences a pointer (`*ptr`), the pointer variable holds a memory address. Register indirect addressing (`LOAD R1, [R2]`) fetches the value at the address stored in R2 — exactly what pointer dereferencing requires. R2 holds the pointer (an address), and the instruction loads the value at that address. This one-to-one correspondence between addressing modes and high-level access patterns is why the modes exist.

Question 4

Immediate mode addressing is the most flexible addressing mode because operands are available instantly without any memory access.

• T. True
• F. False

Answer: False

Immediate mode is the fastest but least flexible. The operand is embedded in the instruction itself, so it must be a compile-time constant that fits in the instruction's operand field — typically a small integer. It cannot represent values stored in registers or memory, and the value cannot change at runtime. The most flexible modes are register indirect and indexed addressing, which can reach any memory location at runtime using values computed during program execution.

Question 5

Explain how the set of addressing modes in an instruction set reflects the data access patterns that programmers need to express in high-level languages.

Model answer: High-level languages require several distinct data access patterns: constants fixed at compile time (→ immediate mode), local variables kept in registers (→ register mode), global variables at fixed addresses (→ direct/absolute mode), pointer dereferencing (→ register indirect), and array or structure field access (→ indexed or scaled indexed mode). Each addressing mode is a hardware primitive that maps to one of these patterns. An ISA lacking indexed mode would need multiple instructions to implement a single array access. The addressing mode set is a design choice about which patterns are common enough to merit dedicated hardware support.

The connection runs in both directions: compiler writers rely on these modes to generate efficient code, and hardware designers add modes when they observe common patterns in compiled code. This is why x86 has evolved increasingly complex addressing modes — they reflect decades of real compiled code patterns.