Questions: Cache Write-Through and Write-Back Policies

Question 1

A program writes to the same memory address 200 times in a tight loop, and the cache line containing that address is never evicted during the loop. How many writes reach main memory under write-back vs. write-through?

• A. Write-back: 200 writes; Write-through: 1 write
• B. Write-back: 1 write (on eviction); Write-through: 200 writes
• C. Both policies generate 200 writes to main memory
• D. Write-back: 0 writes; Write-through: 200 writes (write-back never touches main memory)

Answer: (B)

With write-back, each store updates only the cache line and marks it dirty. Main memory is not touched until eviction. So 200 stores to the same line produce just 1 main-memory write (when the line is eventually evicted). With write-through, every store immediately writes to main memory — 200 stores produce 200 main-memory writes. This bandwidth difference is the core reason write-back dominates in modern processors. Option D is tempting but wrong: write-back does write to main memory eventually, just only on eviction.

Question 2

In a multiprocessor system, why does write-back require explicit cache coherence protocols (like MESI), while write-through is simpler to keep consistent?

• A. Write-back caches are physically farther from main memory in multiprocessor layouts
• B. With write-through, every store propagates to main memory immediately so other cores can observe writes by snooping the memory bus; with write-back, modified data may reside only in one core's cache, invisible to others
• C. Write-through uses dirty bits that must be coordinated across all caches, while write-back does not
• D. Write-back generates more total memory traffic, making coherence harder to track

Answer: (B)

The key issue is visibility. Write-through broadcasts every write to main memory, so any core monitoring the memory bus can see updates as they happen — coherence comes almost for free via bus snooping. Write-back keeps modified data silently in the local cache (the dirty line). Another core that holds a stale copy of the same line has no way of knowing it's outdated without an explicit protocol. MESI (Modified/Exclusive/Shared/Invalid) states track ownership and validity across caches, ensuring that when one core's line is Modified, other cores' copies are invalidated.

Question 3

A dirty bit in a write-back cache indicates that the cache line contains data that has been modified and differs from the corresponding value in main memory.

• T. True
• F. False

Answer: True

The dirty bit is the write-back cache's record-keeping mechanism. When a store updates a cache line, the hardware sets that line's dirty bit to 1. 'Dirty' means the cache holds the authoritative, up-to-date value and main memory holds a stale copy. When the line is evicted, the controller checks the dirty bit: if set, it writes the line back to memory before loading the new line; if clean, the eviction is silent. Without dirty bits, the cache would have no way to distinguish lines that need writing back from those that don't.

Question 4

Write-through caches are generally faster than write-back caches because keeping main memory up to date avoids the overhead of writing back dirty lines on eviction.

• T. True
• F. False

Answer: False

Write-through is generally slower, not faster. Every store instruction generates a write to main memory, which takes hundreds of cycles. Even with a write buffer to absorb some latency, high write traffic saturates the memory bus and stalls the processor. Write-back dramatically reduces memory traffic: if a cache line is written 50 times before eviction, write-back generates 1 memory write while write-through generates 50. The overhead of occasionally flushing a dirty line on eviction is far less than the constant write traffic of write-through.

Question 5

Explain the role of the dirty bit in a write-back cache. What happens when a dirty cache line is evicted, and why does write-back require this mechanism while write-through does not?

Model answer: In a write-back cache, when the CPU stores data to a cache line, only the cache is updated — main memory is not. The dirty bit (one bit per cache line) is set to signal that this line has been modified and its contents differ from main memory. When the cache controller needs to evict a line to make room for new data, it checks the dirty bit: if set, it must first write the modified data back to main memory before loading the new line; if clean, the eviction is silent. Write-through does not need dirty bits because every store immediately writes to both cache and main memory, keeping them always synchronized — eviction never requires a writeback because main memory always has the current value.

The dirty bit is minimal bookkeeping that makes write-back work: instead of writing every store to memory, the cache notes which lines need attention at eviction time. It trades memory bandwidth (fewer writes) for a small amount of hardware bookkeeping and occasional eviction stalls — a tradeoff that pays off enormously in performance.