Questions: Clock Domain Crossing and Synchronization

Question 1

In a two-flip-flop synchronizer, both flip-flops are clocked by the receiving domain's clock. What is the primary purpose of the second flip-flop?

• A. To amplify the signal level of the incoming data to the receiving domain's voltage range
• B. To provide a full clock period for the first flip-flop's potentially metastable output to resolve to a valid logic level before being sampled again
• C. To invert the signal so the receiving domain reads it with the correct polarity
• D. To detect whether metastability occurred and generate an error interrupt for system recovery

Answer: (B)

The first flip-flop samples the incoming signal and may go metastable if the signal arrives near the clock edge. It will eventually resolve to a valid 0 or 1, but the resolution time is probabilistic. The second flip-flop waits an entire clock period — giving the first flip-flop's output time to settle — before capturing the result. This dramatically reduces the probability that a metastable voltage reaches downstream logic. The synchronizer does not eliminate metastability (option D would require that), it reduces the probability to a practically negligible level by buying resolution time.

Question 2

An engineer synchronizes an 8-bit data bus crossing clock domains by connecting each bit through its own independent two-flip-flop synchronizer. Why is this approach insufficient?

• A. Two flip-flops are never adequate — multi-bit buses require at least four flip-flop stages per bit
• B. Each bit may resolve its metastable state at a slightly different time, producing a combined output value that was never actually present in the sending domain
• C. Flip-flop synchronizers work correctly for multi-bit buses; the engineer just needs to ensure all bits have the same propagation delay
• D. The metastability probability multiplies by 8, but otherwise the data value is still correctly transferred

Answer: (B)

Even if each bit eventually resolves correctly, the different bits may resolve at different moments within the clock period, and downstream logic may sample the bus while some bits have resolved and others have not. This produces a corrupted combined value — a 'glitch' that was never a valid state in the sending domain. The correct approach for multi-bit buses is to use an asynchronous FIFO with Gray-coded pointers (where only one bit changes per pointer increment, making single-bit synchronization safe) or a handshake protocol that holds data stable until the receiver acknowledges.

Question 3

Metastability in a flip-flop can be largely eliminated by using a sufficient number of synchronizer flip-flop stages in series.

• T. True
• F. False

Answer: False

Metastability is a physical phenomenon governed by the analog dynamics of flip-flop circuits — specifically, the time constant of the bistable latch's exponential resolution. Each additional synchronizer stage reduces the probability of an unresolved metastable state reaching downstream logic by an exponential factor, but the probability never reaches exactly zero. With two stages, the mean time between failures (MTBF) is typically thousands or millions of years for practical clock frequencies, which is effectively negligible. But 'negligible' is not the same as 'zero' — more stages reduce the probability further at the cost of additional latency.

Question 4

Gray-coded pointers are used in asynchronous FIFOs crossing clock domains because only one bit changes at a time when the pointer increments, making it safe to synchronize the pointer with a single-bit synchronizer.

• T. True
• F. False

Answer: True

A Gray code is a binary encoding where consecutive values differ in exactly one bit. When an FIFO pointer advances by one, only one bit of the Gray-coded pointer changes. A two-flip-flop synchronizer on that single changing bit may go metastable, but even if it temporarily resolves to the wrong value, the resulting pointer represents an adjacent valid state (either the old or new pointer value) — never an arbitrary invalid corruption. This is safe because the FIFO logic can tolerate a one-step error in pointer position (it causes at most a one-entry read/write discrepancy, not data corruption).

Question 5

Why does the standard two-flip-flop synchronizer introduce latency, and why is this latency considered an acceptable tradeoff?

Model answer: The synchronizer introduces latency because the first flip-flop must have a full clock period to resolve from a potentially metastable state before the second flip-flop samples it. This means the synchronized signal reaches the receiving domain two clock cycles after it was generated in the sending domain — one cycle for each flip-flop stage. This latency is acceptable because the alternative is catastrophic: an unresolved metastable voltage propagating into downstream combinational logic produces unpredictable outputs — logic gates receiving an analog mid-supply voltage can behave arbitrarily, causing system-wide failures that are non-deterministic and extremely difficult to debug. Two cycles of deterministic, predictable latency is a small, fixed price for reducing a probabilistic catastrophic failure mode to negligible probability.

This tradeoff illustrates a general principle in digital design: deterministic constraints (latency) are manageable; non-deterministic failures (metastability propagation) are not. When designing across clock domains, the latency budget must account for synchronizer stages — protocols that assume same-cycle data availability will break. Proper clock domain crossing design makes the latency explicit and accounts for it in timing analysis.