Questions: CPU Datapath

Question 1

During the execute stage of a LOAD instruction, what is the ALU computing?

• A. The value to be written to the destination register
• B. The memory address to read from (base register + offset)
• C. The next value of the program counter
• D. The comparison result for a branch condition

Answer: (B)

For a LOAD instruction, the ALU computes the effective memory address by adding the base register value and the signed offset from the instruction. The actual data read from that address is fetched in the memory access stage and then written to the register file in the write-back stage.

Question 2

The datapath decides which instruction to execute next by choosing between control signals.

• T. True
• F. False

Answer: False

The datapath itself does not make decisions — it only moves and transforms data. All routing decisions (which MUX input to select, whether to write a register, etc.) are generated by the control unit based on the decoded opcode. The datapath is purely the hardware mechanism; the control unit is the decision-maker.

Question 3

Why does a single-cycle datapath need to use the longest instruction's execution time as its clock period?

Model answer: Because all instructions must complete within one clock cycle, the clock period must accommodate the slowest path through the datapath — typically a LOAD instruction that uses the ALU, memory, and register write-back in sequence. Faster instructions waste the remaining time each cycle.

In a single-cycle design, every instruction occupies exactly one clock tick regardless of complexity. If the clock were faster than the longest instruction's critical path, that instruction would not finish correctly. The result is that simple instructions like ADD are penalized by the latency of rare complex instructions, which is the key inefficiency that pipelining addresses.