Questions: Introduction to Digital Control Systems

Question 1

A continuous-time PID controller has all poles in the left half s-plane and is stable. It is discretized using forward Euler with a large sampling period T. What would you expect?

• A. The discrete controller remains stable — pole locations in the s-plane determine stability absolutely, regardless of discretization method
• B. The discrete controller may become unstable — large T can map s-plane poles to locations outside the unit circle in the z-plane
• C. The discrete controller is functionally identical to the continuous one — only the notation changes from s to z
• D. Stability is unaffected by sampling rate; only the speed of computation changes

Answer: (B)

This is the most critical misconception in digital control. A stable s-domain pole at s = -a maps to z = e^(-aT) under the exact mapping. For small T, e^(-aT) is safely inside the unit circle. But forward Euler uses the approximation s ≈ (z-1)/T, a cruder mapping that distorts the s-plane-to-z-plane relationship. As T increases, the approximation error grows, and poles that were stable in continuous time may map outside the unit circle — making the discrete controller unstable. Choosing an appropriate sampling rate and discretization method is not optional; it is essential to preserving stability.

Question 2

Why is Tustin's bilinear method (s ≈ (2/T)(z-1)/(z+1)) generally preferred over forward Euler (s ≈ (z-1)/T) for discretizing continuous-time controllers?

• A. Tustin's method requires fewer arithmetic operations per sample, making it faster to execute on microcontrollers
• B. Tustin's method corresponds to the trapezoidal integration rule, better preserving stability margins and frequency-domain accuracy
• C. Tustin's method eliminates the need for anti-aliasing filters before the ADC
• D. Tustin's method maps the s-plane exactly to the z-plane, introducing no approximation error

Answer: (B)

Forward Euler uses a rectangular (left-endpoint) approximation to integration, which is first-order accurate and can push stable poles outside the unit circle. Tustin's bilinear method uses the trapezoidal rule — second-order accurate — and has the crucial property that the entire left half s-plane maps inside the unit circle, so a stable continuous controller always produces a stable discrete controller (though frequency response may be warped). This stability-preservation property makes Tustin the default choice for controller discretization. The tradeoff is frequency warping, which requires pre-warping of critical frequencies before applying the transformation.

Question 3

In a digital control system, stability requires all poles of the discrete-time transfer function H(z) to lie strictly inside the unit circle |z| < 1.

• T. True
• F. False

Answer: True

This is the z-domain analogue of the s-domain stability criterion (all poles in the left half-plane). The mapping between the two domains is z = e^(sT): a stable continuous-time pole at s = -a (left half-plane) maps to z = e^(-aT), which has magnitude e^(-aT) < 1 for positive a — inside the unit circle. Poles on the unit circle (|z| = 1) correspond to marginally stable behavior (undamped oscillation); poles outside are unstable. The unit circle plays exactly the role of the imaginary axis in the s-domain.

Question 4

Digital control is simply analog control implemented in software — the same equations, just computed at discrete time steps rather than continuously.

• T. True
• F. False

Answer: False

Digital implementation introduces new dynamics that do not exist in continuous-time analysis. Computation delay (typically one sample latency between measurement and output) adds a pure delay that degrades phase margin. Quantization error from finite ADC/DAC resolution adds a noise-like signal. Finite word length in the processor can cause limit cycling and coefficient rounding errors. The zero-order hold introduces a half-sample delay in the frequency response. None of these appear in the continuous-time model. A controller that works perfectly in continuous-time simulation may perform noticeably differently as a digital implementation, especially at frequencies approaching half the sampling rate.

Question 5

Why must the sampling rate in a digital control system be much higher than the closed-loop bandwidth, and what happens to controller performance if sampling is too slow?

Model answer: The sampling rate must be high enough that the controller can react to disturbances and errors within a fraction of the system's response time. The Nyquist criterion requires sampling at least twice the highest signal frequency, but in control this is insufficient — the rule of thumb is 5–20 times the closed-loop bandwidth. If sampling is too slow, several problems emerge: the zero-order hold introduces phase lag that erodes stability margins, the controller cannot respond quickly enough to reject disturbances, inter-sample behavior (what the plant does between samples) becomes significant and uncontrolled, and aliasing can fold high-frequency disturbances into the control bandwidth. The result is degraded tracking performance, reduced disturbance rejection, and potentially instability.

A concrete example: a controller with 10 Hz closed-loop bandwidth needs a 50–200 Hz sampling rate. At 50 Hz, the ZOH introduces about 10 ms of average delay (half a sample period), which adds phase lag of approximately 3.6° per Hz of bandwidth — noticeable but manageable. At 10 Hz sampling (only 1× bandwidth), the phase lag becomes catastrophic and the controller may destabilize. This is why choosing the sampling rate is one of the first design decisions in digital control, not an afterthought.