Questions: Digital Logic Gates Basics

Question 1

A designer wants to build a 2-input AND gate in CMOS. They plan to use two transistors (one NMOS, one PMOS) just like a CMOS inverter but rearranged for AND behavior. What is wrong with this plan?

• A. Nothing — a 2-input CMOS AND gate requires exactly two transistors, one NMOS and one PMOS
• B. A CMOS AND gate requires a NAND gate plus an additional inverter stage, meaning it needs more transistors than a 2-input NAND gate
• C. PMOS transistors cannot be used in pull-up networks for multi-input gates
• D. Two transistors are fundamentally insufficient for any gate with more than one input

Answer: (B)

A CMOS inverter (NOT gate) uses one NMOS and one PMOS. A 2-input NAND gate is the natural CMOS primitive: it uses two NMOS in series (pull-down) and two PMOS in parallel (pull-up) — four transistors total. An AND gate is NAND followed by NOT, requiring six transistors total. NAND is simpler to implement than AND in CMOS because AND needs the extra inverter stage. This is why NAND (not AND) is the practical building block of CMOS digital design.

Question 2

A CMOS NAND gate uses NMOS transistors in series in the pull-down network and PMOS transistors in parallel in the pull-up network. What is the arrangement for a CMOS NOR gate?

• A. NMOS in series, PMOS in series
• B. NMOS in parallel, PMOS in parallel
• C. NMOS in parallel, PMOS in series
• D. NMOS in series, PMOS in parallel — the same as NAND

Answer: (C)

NAND and NOR are duals in CMOS. NAND: pull-down NMOS in series (output goes LOW only when ALL inputs are HIGH), pull-up PMOS in parallel (output goes HIGH if ANY input is LOW). NOR reverses both networks: pull-down NMOS in parallel (output goes LOW if ANY input is HIGH), pull-up PMOS in series (output goes HIGH only when ALL inputs are LOW). This dual structure follows directly from De Morgan's theorem: NOR(A,B) = NOT(A OR B), which is the complement of NAND's logic.

Question 3

AND and OR are the most fundamental gates in CMOS hardware because most Boolean logic can be built from them.

• T. True
• F. False

Answer: False

While AND, OR, and NOT form a logically complete set, NAND and NOR are the natural primitives in CMOS hardware. A CMOS NAND gate is simpler to build than an AND gate (AND = NAND + inverter, requiring an extra transistor stage). Similarly, NOR is simpler than OR. In practice, CMOS implementations use NAND and NOR as primitives and construct AND/OR by adding inverters. The statement that AND and OR are 'most fundamental in hardware' is a common misconception — they are logically fundamental but not the simplest to implement in CMOS.

Question 4

In a CMOS gate, no static current flows between V_DD and ground while the output is held at a steady HIGH or LOW state.

• T. True
• F. False

Answer: True

This is the defining advantage of CMOS. Every CMOS gate is designed so that when the output is stable, exactly one transistor in the pull-up/pull-down network is fully OFF, blocking the path from V_DD to ground. In a CMOS inverter, when input is HIGH: NMOS is ON (output pulled to ground) but PMOS is OFF (no path from V_DD). When input is LOW: PMOS is ON but NMOS is OFF. The complementary design ensures zero static current. Current only flows transiently during switching, which is why power dissipation in CMOS scales with clock frequency rather than with the number of gates held at steady state.

Question 5

Why do CMOS circuits draw significant current only during switching transitions, and why is this critical for modern chip design?

Model answer: CMOS uses complementary NMOS and PMOS transistors designed so that exactly one is always OFF during steady state, blocking any static current path between V_DD and ground. Current only flows transiently while the output switches, as both transistors briefly conduct during the transition interval. This is critical because a modern processor contains billions of transistors. If each drew even a tiny static current, the aggregate heat dissipation would be catastrophic and unsustainable. CMOS's zero static power means total chip power scales primarily with switching frequency and capacitance (dynamic power: P = α·C·V²·f), not with transistor count at rest — enabling the dense, high-transistor-count chips that underlie all modern computing.

The alternative, earlier technologies like NMOS-only logic, had a pull-down transistor and a resistive pull-up, meaning static current flowed whenever the output was LOW. This made large-scale NMOS chips hot and power-hungry. CMOS's complementary design solved this, which is why it became the dominant technology for digital integrated circuits.