Questions: Direct Memory Access (DMA) Controllers and Design

Question 1

Using DMA, a disk controller transfers 4 KB of data to memory. How many times is the CPU directly involved in the individual word-by-word data transfer?

• A. Zero — the DMA controller handles all word transfers autonomously; the CPU is only involved in initial setup and the final completion interrupt
• B. Once per byte, since memory write operations always require a CPU instruction
• C. Once per 4-byte word, for each load-store operation
• D. Twice — once at the start of each disk sector and once when the buffer fills

Answer: (A)

This is the defining feature of DMA. After the CPU programs the DMA controller (source address, destination address, byte count, direction), the DMA controller independently manages every individual word transfer — reading from the device, writing to memory, incrementing the address register, and decrementing the count — without any CPU instruction per word. The CPU is interrupted exactly once, when the count reaches zero and the transfer is complete. This is why DMA is so much more efficient than interrupt-driven I/O for large transfers.

Question 2

In cycle-stealing DMA mode, what happens to the CPU during the data transfer?

• A. The CPU is briefly stalled for one bus cycle per word transferred but can otherwise continue executing between steals
• B. The CPU is completely halted for the entire duration of the transfer
• C. The CPU runs at half clock speed to share bus bandwidth with the DMA controller
• D. The CPU is completely unaffected — cycle stealing uses a dedicated DMA bus that does not contend with the CPU

Answer: (A)

In cycle stealing, the DMA controller 'borrows' individual bus cycles from the CPU — one stall per word transferred. Between steals, the CPU resumes execution normally. This contrasts with burst mode, where the DMA controller takes exclusive bus control for the entire transfer (CPU halted throughout), and transparent mode, where the DMA controller only uses the bus during cycles the CPU is not accessing memory (no stall at all, but slower). Cycle stealing is a middle ground: some CPU stall, but execution continues between transfers.

Question 3

After programming a DMA controller to perform a transfer, the CPU can execute other instructions while the transfer is in progress.

• T. True
• F. False

Answer: True

True — this is the primary performance benefit of DMA. Once the CPU writes the source address, destination address, byte count, and direction to the DMA controller's registers, it is free to execute other code. The DMA controller independently manages the bus cycles required to complete the transfer. The CPU is not involved again until it receives the completion interrupt. This overlap of I/O and computation is what enables high-bandwidth I/O without sacrificing CPU throughput.

Question 4

DMA eliminates the need for interrupts largely, since the data transfer occurs without CPU involvement.

• T. True
• F. False

Answer: False

False. DMA does not eliminate interrupts — it dramatically reduces their number. Without DMA (interrupt-driven I/O), the device raises one interrupt per word transferred, potentially thousands for a large block. With DMA, the DMA controller raises exactly one interrupt at the end of the entire transfer to notify the CPU of completion. The completion interrupt is essential: without it, the CPU would not know when the data is ready and would have to poll the DMA controller's status register, which is inefficient. DMA replaces thousands of fine-grained interrupts with one coarse-grained one.

Question 5

Explain why DMA dramatically improves I/O throughput compared to interrupt-driven I/O for large data transfers.

Model answer: In interrupt-driven I/O without DMA, the device raises one interrupt per word transferred. Each interrupt requires saving CPU registers, executing an interrupt handler that performs the load-store, and restoring state — tens to hundreds of CPU cycles per word. For a 4 KB block, this means thousands of interrupts and nearly all CPU time spent on data movement, leaving little for useful computation. DMA replaces this with one programmed setup (writing to DMA registers) and one completion interrupt at the end. The DMA controller handles all address incrementing and memory writes autonomously, and the CPU runs application code throughout the entire transfer.

The key insight is that the bottleneck in interrupt-driven I/O is not the memory bandwidth — it is the per-word CPU overhead. DMA offloads this overhead to dedicated hardware. Modern systems exploit this further with scatter-gather DMA, which can transfer data to or from non-contiguous memory regions in a single programmed operation, and with multiple independent DMA channels managing different I/O streams simultaneously.