Questions: Dynamic RAM (DRAM) Organization and Refresh Cycles

Question 1

A CPU performs a read operation on a DRAM row. After the data is returned to the CPU, what has happened to the charge on the capacitors in that row?

• A. The capacitors retain their original charge — DRAM reads are non-destructive
• B. The capacitors discharge during the read; sense amplifiers latch the values and the row is automatically rewritten
• C. Only the accessed cells discharge; unaccessed cells in the same row retain their charge
• D. The capacitors are refreshed before the read to guarantee data integrity

Answer: (B)

DRAM reads are destructive. When a row is activated, all cells dump their charge onto the shared bit lines — the sense amplifiers detect the tiny voltage difference, latch the values, and then immediately write them back to restore the charge. This implicit rewrite is why row activation counts as a refresh for that row. The destruction of the original charge is an unavoidable consequence of the sense amplifier architecture.

Question 2

Why does DRAM use address multiplexing — sending row and column addresses in two separate cycles on the same pins — instead of sending the full address at once?

• A. It reduces latency by allowing the row and column decoders to work simultaneously
• B. It halves the number of address pins required, keeping the package compact and inexpensive
• C. It allows the memory controller to refresh rows between address cycles
• D. It prevents timing conflicts between read and write operations on the same row

Answer: (B)

Address multiplexing is a cost and packaging decision. A DRAM with 1 GB of addressable memory would need 30 address lines to send the full address at once. By sending the row address first (latched by the Row Address Strobe) and column address second (latched by the Column Address Strobe) on the same pins, the pin count is cut roughly in half. This makes DRAM chips physically smaller and cheaper — the tradeoff is the added latency of two address cycles per access.

Question 3

DRAM cells must be periodically refreshed because their storage capacitors gradually lose charge and will eventually become unreadable without intervention.

• T. True
• F. False

Answer: True

This is the fundamental characteristic that makes DRAM 'dynamic.' A capacitor leaks charge through the transistor and surrounding silicon even when no operation is occurring. Without refresh, stored values degrade within milliseconds. Modern DRAM must refresh every row within a 64-millisecond window. Each refresh cycle consumes memory bus bandwidth, making refresh overhead a constant performance tax.

Question 4

DRAM achieves higher storage density than SRAM because it uses a more sophisticated multi-transistor cell that packs more tightly into silicon.

• T. True
• F. False

Answer: False

DRAM achieves higher density because its cell is simpler, not more sophisticated. A DRAM cell uses one transistor and one capacitor (1T1C). An SRAM cell uses six transistors (6T) arranged in a feedback loop to hold state without refresh. Fewer transistors per bit means more bits per unit area — DRAM is denser because it is simpler, not despite being simpler.

Question 5

Why does DRAM require periodic refresh even when no data is being read or written, and what is the performance cost of this requirement?

Model answer: A DRAM capacitor leaks charge passively — charge dissipates through the transistor even with no active operation. Left unattended, stored values become unreadable within milliseconds. Refresh circuits must periodically activate every row in the array (reading and rewriting all cells) within a fixed window, typically 64 ms. Each refresh cycle occupies the memory bus, preventing normal read and write accesses during that time. This creates a constant bandwidth tax: some fraction of all memory cycles are consumed by refresh overhead, reducing the effective memory bandwidth available to the processor. This overhead, combined with the multi-step row/column addressing, is why DRAM latency is fundamentally higher than SRAM.

The refresh requirement is the defining tradeoff of DRAM design: you get 6× or more the storage density compared to SRAM, at the cost of refresh overhead and slower access. The memory hierarchy — SRAM caches close to the CPU, DRAM main memory farther away — exists precisely to hide this latency difference.