Questions: Exception and Interrupt Handling Architecture

Question 1

A page fault fires while an instruction is partway through execution in a pipelined processor. The OS loads the missing page and returns. What must the processor guarantee for this sequence to work correctly?

• A. The faulting instruction is skipped and execution resumes at the next instruction.
• B. The processor must guarantee precise exception semantics: all prior instructions appear complete, the faulting instruction appears as if it never started, and it will be re-executed from scratch after the handler returns.
• C. The pipeline flushes all in-flight instructions and the program restarts from its beginning.
• D. The exception handler runs within the same pipeline stage where the fault was detected.

Answer: (B)

Precise exceptions require the processor to present a clean architectural state at the point of the fault: all instructions before the faulting one have completed their effects, and no effects of the faulting instruction or any instruction after it are visible. The faulting instruction is then re-executed once the OS has fixed the problem. This is essential for virtual memory — the instruction must be able to succeed on the second attempt. Option A would silently skip a computation; option C would destroy all prior work; option D misunderstands where handlers execute.

Question 2

When a keyboard interrupt arrives, the processor indexes into the interrupt vector table using the interrupt's type number. What does the table entry at that index contain?

• A. A saved copy of the interrupted program's register values.
• B. A priority level number indicating whether the interrupt should preempt the current handler.
• C. The memory address of the handler routine to be executed for this interrupt type.
• D. A flag indicating whether the I/O device has already been acknowledged.

Answer: (C)

The interrupt vector table is an array of handler addresses indexed by exception type. When the processor receives interrupt type N, it loads the address stored at entry N and jumps to that handler. This is how the processor knows where to find the keyboard handler, the page fault handler, the divide-by-zero handler, and so on — each type maps to a distinct handler address. Register saving (option A) typically happens before the table lookup, pushed onto a kernel stack or into dedicated registers.

Question 3

Achieving precise exceptions in a pipelined processor requires flushing partially-completed instructions that followed the faulting instruction and restoring the architectural state to the exact point of the fault.

• T. True
• F. False

Answer: True

True. In a pipeline, multiple instructions are in flight simultaneously. When an exception fires, instructions younger than the faulting instruction may have partially modified registers or memory. Precise exceptions require squashing all of these in-progress effects and rolling the architectural state back to the exact snapshot before the faulting instruction began. This is one of the most demanding aspects of processor design, particularly for out-of-order and deeply pipelined processors.

Question 4

After an exception handler finishes, the processor generally resumes execution at the instruction immediately following the one that caused the exception.

• T. True
• F. False

Answer: False

False — whether to resume at the same instruction or the next depends on the exception type. For faults (page faults, divide-by-zero), the handler corrects the problem and the processor re-executes the faulting instruction — resuming at the next instruction would skip it and lose its result. For traps (intentional software interrupts like system calls), execution resumes at the instruction after the trap. The processor saves either the faulting PC or PC+1 depending on the exception class, and the handler uses this to determine where to return.

Question 5

Why do pipelined processors face a significantly harder problem achieving precise exceptions than single-cycle processors?

Model answer: In a single-cycle processor, exactly one instruction is in flight at a time — when an exception fires, no other instruction has been partially modified, so the processor simply saves the PC and jumps to the handler. In a pipelined processor, multiple instructions are simultaneously in different stages. If instruction I faults at stage 4, instructions I+1 and I+2 may already be in earlier stages having partially read or written registers. Achieving precise exceptions requires detecting the fault, preventing younger instructions from committing their results, and restoring the architectural state to the snapshot before instruction I — all without losing the pipeline's throughput advantage.

Out-of-order processors face an even harder version: instructions may complete out of order, so maintaining a precise exception point requires re-order buffers that track which results have been architecturally committed versus speculatively executed. This hardware complexity is the direct cost of supporting precise exceptions in high-performance designs — but it is a cost modern processors pay because virtual memory and debuggers depend on it.