Questions: Flip-Flops and Latches

Question 1

A D latch has its enable signal held high for 100 nanoseconds while the D input toggles between 0 and 1 multiple times. What does the output Q do during this period?

• A. Q remains at the value captured when enable first went high
• B. Q changes only at the end of the enable pulse, capturing the final D value
• C. Q continuously tracks the D input — the latch is transparent while enable is high
• D. Q enters an indeterminate state because D is changing

Answer: (C)

A latch is level-sensitive: while enable is high, the output Q continuously follows the D input — this is called being 'transparent.' This is the fundamental distinction from a flip-flop. A D flip-flop would capture D only at the rising (or falling) clock edge and hold it regardless of subsequent D changes. The transparency of latches is what makes them problematic in synchronous design: signals can 'race' through multiple latches in a single clock phase.

Question 2

A D flip-flop's D input changes value 10 nanoseconds before the rising clock edge and remains stable for 5 nanoseconds after. The setup time is 8 ns and hold time is 3 ns. What happens?

• A. The flip-flop correctly captures the new D value — both setup and hold times are satisfied
• B. The flip-flop enters metastability — the setup time requirement is violated
• C. The flip-flop captures the old D value — data that arrives that late cannot be captured
• D. The flip-flop enters metastability — the hold time requirement is violated

Answer: (A)

Setup time requires D to be stable for 8 ns before the clock edge — D changed 10 ns before the edge, so it has been stable for 10 ns (satisfied). Hold time requires D to remain stable 3 ns after the clock edge — it stays stable 5 ns after (satisfied). Both constraints are met, so the flip-flop correctly captures the new D value. Metastability only occurs when D changes too close to or during the clock edge, violating setup or hold time.

Question 3

The clock signal in a synchronous circuit is what maintains the stored bit value in a flip-flop between clock edges.

• T. True
• F. False

Answer: False

The bit value is maintained by the internal feedback loop, not by the clock. Between clock edges, the clock may be low, but the stored value is held by the cross-coupled feedback in the circuit — the same mechanism as the SR latch. The clock's role is to control WHEN a new value is captured. Once captured, the feedback loop holds the value independently of what the clock is doing.

Question 4

Edge-triggered flip-flops are preferred over level-sensitive latches for synchronous digital design.

• T. True
• F. False

Answer: True

Edge triggering gives precise, predictable state changes synchronized to a single moment per clock cycle. Level-sensitive latches are 'transparent' whenever enable is high, creating windows where signals can race through multiple stages unexpectedly. Synchronous design requires that all state changes happen at known, coordinated moments so that timing analysis is tractable. Flip-flops, by sampling exactly at the clock edge, make timing analysis well-defined: signals must be stable within the setup/hold window, and propagation delays are bounded by the clock period.

Question 5

Explain how the feedback structure inside a flip-flop allows it to maintain a stored value indefinitely between clock edges.

Model answer: The flip-flop contains a cross-coupled feedback loop (inherited from the SR latch) where the output of each gate feeds back into the input of the other. This creates two stable states: Q=1,Q̄=0 and Q=0,Q̄=1. Once the circuit settles into one state, the feedback reinforces itself — each gate's output keeps the other gate in a consistent state. This self-reinforcing loop persists regardless of what happens at the data input or clock, holding the bit until the next active clock edge causes the circuit to capture a new value.

Feedback is what distinguishes sequential circuits from combinational ones. In a combinational circuit, outputs are functions of current inputs only. In a bistable flip-flop, the feedback loop is the storage mechanism: it creates memory that persists even when inputs change. The clock edge momentarily connects the data input to the feedback loop, updating the stored value, then the loop closes again to hold the new state. This also explains why setup/hold times matter: if D changes during the capture window, the feedback loop receives inconsistent inputs and can enter a metastable state between 0 and 1.