Questions: Half Adder Circuit Design

Question 1

A half adder receives inputs A=1 and B=1. What are the sum and carry outputs?

• A. Sum=0, Carry=1
• B. Sum=1, Carry=0
• C. Sum=1, Carry=1
• D. Sum=0, Carry=0

Answer: (A)

1+1 in binary equals 10 (decimal 2): a sum bit of 0 and a carry bit of 1. The XOR gate (sum) outputs 0 when both inputs are identical; the AND gate (carry) outputs 1 when both inputs are 1. This is the one case where the carry is generated.

Question 2

Why can't half adders alone be chained to build a multi-bit binary adder?

• A. Because XOR gates cannot be cascaded in sequence
• B. Because a half adder has no carry-in input to accept a carry from the previous bit position
• C. Because a half adder produces two outputs, which confuses downstream gates
• D. Because AND gates are too slow for multi-bit arithmetic

Answer: (B)

Every bit position beyond the least significant must handle a potential carry arriving from the column to its right. A half adder only accepts two inputs (A and B) — it has nowhere to plug in an incoming carry. The full adder solves this by adding a third input (carry-in), allowing it to be placed in any bit position. The half adder can only correctly handle the rightmost bit, where there is no prior carry.

Question 3

In a half adder, the XOR gate produces the carry bit and the AND gate produces the sum bit.

• T. True
• F. False

Answer: False

The assignments are reversed. The XOR gate produces the sum bit — it outputs 1 exactly when the two inputs differ (one 1 and one 0), which matches the sum column of the addition truth table. The AND gate produces the carry bit — it outputs 1 only when both inputs are 1, which is the only case where a carry is generated (1+1=10).

Question 4

A half adder is sufficient for the second-least-significant bit position (bit 1) of a multi-bit adder, since carries primarily propagate from that position forward.

• T. True
• F. False

Answer: False

Bit position 1 must accept a possible carry-out from bit position 0. A half adder has no carry-in input, so it cannot incorporate that carry — it would silently drop it, producing wrong results. Only the least significant bit (bit 0) can use a half adder; all higher positions require full adders that accept carry-in.

Question 5

Why does XOR implement the sum bit and AND implement the carry bit in a half adder? Explain in terms of what each gate computes.

Model answer: XOR outputs 1 when its inputs differ — exactly when one input is 1 and the other is 0, giving a sum of 1 with no carry. AND outputs 1 only when both inputs are 1, the case that produces a sum of 0 and a carry of 1. Together they replicate the complete truth table for 1-bit binary addition: 0+0=00, 0+1=01, 1+0=01, 1+1=10.

The elegance of the half adder is that the truth tables of XOR and AND perfectly match the two output columns (sum, carry) of single-bit binary addition. No complex logic is needed — the arithmetic structure and the gate structure coincide exactly. This mapping is why single-bit addition requires only two gates and is the foundational building block from which all larger adder circuits are constructed.