The processor is about to fetch the next instruction. What does it do, and how does it know where to look?
AIt asks the operating system which instruction to run next
BIt reads the next instruction from the memory address in the program counter (PC), then increments the PC
CIt examines the instruction register (IR) to determine which memory address to fetch from
DIt broadcasts a request to all memory banks and uses the first response
The program counter holds the address of the next instruction to execute. During fetch, the processor reads instruction bytes from that address into the instruction register (IR), then auto-increments the PC to point to the next sequential instruction. The PC is the bookmark; fetch reads it and advances it. The instruction register holds what was just read, not a pointer to what to read next.
Question 2 Multiple Choice
The processor has decoded a branch instruction: 'if zero flag is set, jump to address 0x200.' The zero flag is set. What happens during execute?
AThe ALU performs a subtraction and stores the result in a register
BThe processor loads data from memory address 0x200 into a general-purpose register
CThe PC is overwritten with 0x200, redirecting the next fetch to that address instead of the default sequential next instruction
DThe instruction is placed back in the instruction register to be re-decoded at the new address
Branch instructions work by overwriting the PC during execute. The next fetch phase will then retrieve the instruction at 0x200 rather than the auto-incremented sequential address. This is the only mechanism by which programs deviate from sequential execution — without the ability to overwrite the PC, no loops, conditionals, or function calls would be possible.
Question 3 True / False
The decode phase determines what operation to perform, but the selection of which registers or memory addresses to use happens later, during the execute phase.
TTrue
FFalse
Answer: False
Decode determines both the operation AND the operands — which registers to read, which memory addresses to access, and which ALU function to select. The control unit translates all instruction bits into all necessary internal signals during decode. Execute then carries out that already-decoded plan; it doesn't make new interpretations. Decode is parsing; execute is acting on the parsed result.
Question 4 True / False
A branch instruction changes the program counter to a new address, which is why the instruction executed immediately after a taken branch is not the one that follows it in memory.
TTrue
FFalse
Answer: True
The PC auto-increments during every fetch, so by default programs execute in sequential memory order. A branch's execute phase overwrites the PC with the branch target address. The *next* fetch therefore retrieves from that target, not from the next sequential address. This is the fundamental mechanism behind all non-sequential control flow: loops, if-statements, function calls, and returns.
Question 5 Short Answer
Why is the program counter (PC) central to the fetch-decode-execute cycle, and how do branch instructions exploit it?
Think about your answer, then reveal below.
Model answer: The PC acts as a pointer tracking which instruction to execute next. During every fetch, the processor reads from the address in the PC and then auto-increments it to point to the next sequential instruction — this is how sequential execution happens automatically. Branch instructions exploit the PC by overwriting it during execute with a new address (the branch target). The next fetch retrieves from the branch target rather than the sequential next, implementing loops, conditionals, and function calls.
Every non-sequential behavior in a program — including function calls (which overwrite the PC with the function's first instruction and push the return address so it can be restored later) — is ultimately an overwrite of the PC. The PC's auto-increment gives you sequential execution for free; branches are deliberate overrides of that default.