Questions: Interrupts and Direct Memory Access (DMA)

Question 1

A keyboard generates one keystroke every 50 milliseconds. With polling, the CPU checks the keyboard status register every 1 millisecond. What is the primary advantage of switching to interrupt-driven I/O?

• A. The keyboard can process keystrokes faster because it no longer waits for the CPU to check
• B. The CPU is freed to execute other instructions between keystrokes instead of spinning in a polling loop
• C. Interrupts eliminate the need to save and restore CPU state when handling device events
• D. The CPU can handle multiple devices simultaneously without any performance overhead

Answer: (B)

With polling, the CPU wastes the vast majority of its cycles checking a status register that almost always says 'not ready.' Interrupt-driven I/O inverts the relationship: the device signals the CPU only when it has something to report, freeing the processor to do useful work in between. Option C is wrong — saving and restoring state is a cost of interrupts, not an elimination. The key insight is that polling wastes CPU time proportional to how often you check; interrupts spend CPU time proportional to how often events actually occur.

Question 2

A disk controller needs to transfer 16 KB of data from disk to RAM. Comparing interrupt-driven I/O (one interrupt per byte) versus DMA, what is the primary advantage of DMA?

• A. DMA bypasses the memory bus entirely, so CPU memory accesses are completely unaffected during the transfer
• B. DMA eliminates the need for the CPU to set up the transfer — the disk controller handles everything autonomously
• C. DMA reduces the number of CPU interrupts from thousands (one per byte) to a single completion interrupt
• D. DMA transfers data faster than interrupt-driven I/O because the DMA controller uses a dedicated high-speed bus

Answer: (C)

The core advantage of DMA is drastically reducing CPU involvement. For a 16 KB transfer, interrupt-driven I/O would generate 16,384 separate interrupts — each requiring the CPU to save state, run the ISR, and restore state. DMA offloads the entire bulk transfer to a dedicated controller, which performs the move autonomously and generates exactly one interrupt when done. Option A is false — DMA uses the same memory bus as the CPU (cycle stealing), so CPU accesses are slightly slowed. Option B is false — the CPU must still set up the DMA transfer parameters.

Question 3

An interrupt is triggered by the instruction currently executing in the CPU, while an exception is triggered by an external hardware device.

• T. True
• F. False

Answer: False

This has the definitions exactly reversed. An interrupt is asynchronous — it is triggered by an external hardware device (keyboard, disk, network card) at an unpredictable moment, unrelated to the current instruction. An exception is synchronous — it is triggered by the instruction itself (divide-by-zero, invalid memory access, page fault). Both use similar handler mechanisms, but their causes are fundamentally different: interrupts come from outside, exceptions come from inside.

Question 4

After an interrupt service routine completes, the interrupted program resumes execution exactly where it was paused, with all register state restored.

• T. True
• F. False

Answer: True

True. This transparent resumption is essential to how interrupts work correctly. When an interrupt arrives, the CPU finishes the current instruction, saves the program counter and registers to a stack, executes the ISR, then executes a 'return from interrupt' instruction that restores the saved state. The interrupted program has no way of knowing an interrupt occurred — it resumes from the exact instruction it would have executed next. This is why interrupts can handle device events without corrupting the execution of arbitrary user programs.

Question 5

Explain why polling is less CPU-efficient than interrupt-driven I/O, and describe the step-by-step sequence from when a device needs service to when the CPU resumes its original work.

Model answer: Polling wastes CPU cycles because the processor must repeatedly check a device status register regardless of whether the device is ready — most checks find 'not ready' and discard the result. Interrupt-driven I/O is efficient because the CPU only responds when there is actually something to handle. The interrupt sequence: (1) device signals the CPU's interrupt pin when it needs service; (2) CPU finishes the current instruction; (3) CPU saves the program counter and key registers to a stack; (4) CPU jumps to the pre-defined interrupt service routine (ISR); (5) ISR handles the device event (e.g., reads a byte, acknowledges a transfer); (6) ISR executes 'return from interrupt'; (7) CPU restores saved registers and PC; (8) original program resumes from where it was paused.

The efficiency difference is especially stark for slow devices. A disk might take milliseconds to complete an operation — during which time a polling CPU checks the status register thousands of times, accomplishing nothing. An interrupt-driven CPU runs other processes for those milliseconds and handles the disk event in a single well-timed ISR invocation.