Questions: I/O Systems and Buses

Question 1

A programmer uses a standard store instruction to write to address 0xFFFE0010 and successfully configures a graphics card register. Which I/O model does this describe?

• A. Port-mapped I/O — the OUT instruction is implicitly called by the compiler
• B. Memory-mapped I/O — device registers occupy reserved addresses in the main address space
• C. Direct Memory Access — the CPU is bypassed and the device writes directly to RAM
• D. Interrupt-driven I/O — the device signals the CPU when it is ready

Answer: (B)

Memory-mapped I/O is the key: device control registers are assigned addresses within the same address space as regular memory, so ordinary load/store instructions interact with devices — no special instructions needed. Port-mapped I/O requires dedicated IN/OUT instructions and a separate I/O address space. DMA and interrupt-driven I/O are different mechanisms for handling data transfer and timing, not the fundamental addressing model being described here.

Question 2

A slow hard drive transfers data at 100 MB/s while the system bus operates at 8 GB/s. Which component primarily bridges this speed mismatch?

• A. The CPU cache, which stores recently accessed disk data for fast retrieval
• B. The device controller, which buffers data from the peripheral before transferring it in bursts to the bus
• C. The OS scheduler, which pauses the CPU while waiting for disk data
• D. Port-mapped I/O, which provides a dedicated channel for slow devices

Answer: (B)

The device controller bridges the speed mismatch by accumulating data from the slow peripheral and then transferring it to the system bus in bursts when a meaningful chunk is ready. This prevents the CPU from waiting one byte at a time for a device 80x slower than the bus. CPU caches handle processor-memory latency, not peripheral-bus mismatches. OS schedulers manage CPU time but don't solve the underlying hardware speed gap. Port-mapped I/O is an addressing scheme, not a buffering solution.

Question 3

In memory-mapped I/O, device registers occupy the same address space as physical RAM, which reduces the total memory available to programs.

• T. True
• F. False

Answer: False

Memory-mapped I/O assigns addresses in the CPU's address space to device registers, but those addresses do not correspond to physical DRAM chips — they're reserved ranges that hardware routes to device controllers. Programs cannot use those addresses for normal memory, but the physical RAM is not reduced. The CPU's address space is a logical construct; memory-mapped I/O occupies parts of that logical space without consuming physical memory.

Question 4

A bus can be understood as simply a collection of wires connecting the CPU to peripheral devices.

• T. True
• F. False

Answer: False

A bus is a shared communication pathway that includes a protocol — rules for arbitration (deciding which device can use the bus when multiple want to simultaneously), timing (synchronizing data transfer), and error detection. Without arbitration, two devices transmitting simultaneously would corrupt each other's signals. The wires are the physical medium; the bus protocol is what makes communication reliable and orderly. This distinction matters when comparing buses: PCIe, USB, and SATA differ not just in wire count but in their protocols, bandwidth, and arbitration mechanisms.

Question 5

Explain why device controllers are necessary in an I/O system, even when the CPU could theoretically poll devices directly.

Model answer: Device controllers buffer data between slow peripherals and the fast system bus, preventing the CPU from being forced to wait for each byte one at a time. They translate between the bus protocol and device-specific interfaces, handle error detection, and accumulate data until a useful chunk is ready for transfer. Without them, the CPU would waste enormous time busy-waiting for devices thousands of times slower than itself, or every peripheral would need to match CPU speeds — both impractical.

The speed mismatch is the fundamental driver. A keyboard generates data at human typing speeds (~10 characters/second); the CPU operates at billions of cycles per second. A controller buffers keystrokes so the CPU can handle them in bursts when interrupted, rather than polling constantly. This buffering model also motivates DMA (Direct Memory Access) for high-bandwidth devices: by removing the CPU from the data path entirely, DMA frees the processor for computation while the controller manages large transfers autonomously.