A DRAM module has an access time of 50 ns. After reading, the bit lines must be precharged before another access can begin. The total cycle time is 100 ns. A program issues back-to-back read requests as fast as possible. What limits the effective memory bandwidth?
AAccess time, because that determines how long each read takes
BCycle time, because the precharge phase must complete before a new access starts
CThe processor speed, because the CPU cannot issue requests faster than 50 ns
DThe address bus width, because wider buses reduce decoding delay
Cycle time — not access time — is the limiting factor for sustained memory bandwidth. Even though valid data appears after 50 ns (access time), the memory cannot begin another access until the bit lines are recharged, adding another 50 ns. This precharge requirement means the memory can only accept one request every 100 ns. Access time tells you the latency of a single read; cycle time tells you the throughput ceiling for successive reads.
Question 2 Multiple Choice
A processor executes one instruction per nanosecond. Each instruction requires one memory access. If main DRAM has an access time of 60 ns, approximately how many instructions does the processor complete per second assuming no caching?
A1 billion — the processor speed determines throughput
BAbout 16.7 million — memory latency limits throughput to roughly 1 access per 60 ns
CAbout 500 million — memory and CPU share the bottleneck equally
DIt depends on the instruction mix, not memory speed
Without a cache, every instruction requires waiting for DRAM. At 60 ns per access, the processor can complete at most 1/60×10⁻⁹ ≈ 16.7 million instructions per second — far below its 1 billion/sec capability. This two-order-of-magnitude gap is the 'memory wall.' The processor's speed is irrelevant when it spends nearly all its time waiting. This is precisely why caches exist: to serve most requests from fast SRAM and make the slow DRAM access rate nearly invisible.
Question 3 True / False
Access time and cycle time are the same quantity, just measured from different reference points in the memory access sequence.
TTrue
FFalse
Answer: False
They are distinct quantities. Access time is the delay from issuing a read request to receiving valid data on the data bus. Cycle time is the minimum interval between the start of successive accesses — it equals access time plus the precharge delay needed to reset bit lines. Cycle time is always larger than access time. Conflating them leads to overestimating memory bandwidth: knowing access time alone tells you latency but not how quickly back-to-back accesses can proceed.
Question 4 True / False
The fundamental reason caches improve performance is that they exploit locality — the tendency for programs to reuse recently accessed data — to serve most requests at nanosecond speeds instead of waiting tens of nanoseconds for DRAM.
TTrue
FFalse
Answer: True
This is exactly right. Caches work because most memory accesses cluster around recently or nearby used locations (temporal and spatial locality). A small, fast SRAM cache captures these hot data items so the processor rarely needs to pay the full DRAM access time. Without locality, a cache would offer no benefit — every access would miss and fall through to slow DRAM. Understanding access time and cycle time explains why the cache hit/miss distinction matters so much: a hit costs nanoseconds, a miss costs tens of nanoseconds.
Question 5 Short Answer
Explain why cycle time is larger than access time in DRAM, and describe what implication this has for memory bandwidth.
Think about your answer, then reveal below.
Model answer: Cycle time exceeds access time because after a read, the memory's bit lines must be precharged — restored to a neutral voltage — before another row can be selected and another access started. Access time only covers request-to-data-valid; cycle time covers the full period until the memory is ready for the next request. The implication is that memory bandwidth (accesses per second) is bounded by 1/cycle_time, not 1/access_time, and is therefore lower than the latency figure alone would suggest.
The precharge step is an inherent property of DRAM cell design: reading destroys the charge on a capacitor cell, which must be refreshed. This refresh happens at the row level, requiring all bit lines in a row to settle before the next access. The distinction matters for architects designing memory systems: you can partially hide access time with pipelining, but cycle time sets a hard throughput ceiling. Techniques like burst mode (reading multiple consecutive words in one cycle) and bank interleaving (multiple DRAM banks precharged in rotation) exist specifically to work around this constraint.