A memory chip requires a 12-bit address. Compared to using a single flat 12-to-4096 decoder, two-dimensional decoding (6 row bits + 6 column bits) requires how many total decoder output lines?
A4,096 — 2D decoding saves internal wiring but the number of output lines stays the same
B128 — 64 from the row decoder plus 64 from the column decoder
C2,048 — exactly half as many as the flat decoder
D24 — two output lines per address bit
A single flat 12-to-4096 decoder needs 4,096 output lines — one per possible address. 2D decoding splits the 12-bit address into two 6-bit halves, requiring a 6-to-64 row decoder (64 outputs) and a 6-to-64 column decoder (64 outputs): 128 lines total instead of 4,096. This is the core efficiency gain of 2D decoding — the output count grows as 2 × 2^(n/2) rather than 2^n.
Question 2 Multiple Choice
What is the consequence of 'partial decoding' in a memory system?
AMemory access becomes slower because fewer address bits are checked
BThe same physical memory location appears at multiple addresses, called aliasing
CCertain memory addresses become permanently inaccessible
DMemory chips using partial decoding cannot correctly store all data patterns
Partial decoding ignores some address bits, meaning multiple distinct addresses map to the same physical location. For example, if bit 15 is ignored, addresses 0x0100 and 0x8100 both select the same memory cell. This 'aliasing' wastes address space but reduces hardware complexity. Early microcomputers used this tradeoff deliberately; modern systems use full decoding to avoid wasting the address space.
Question 3 True / False
In a 2D decoded memory with a 10-bit address split into 5 row bits and 5 column bits, each row in the memory array contains 32 cells that share the same row-select signal.
TTrue
FFalse
Answer: True
With 5 row bits, the row decoder has 2^5 = 32 output lines, one per row. Each row contains 2^5 = 32 cells (one per column). When a row line is asserted, all 32 cells in that row are electrically accessed simultaneously — this is why DRAM, which uses a similar scheme, has a separate row-access strobe (RAS) and column-address strobe (CAS) phase in its timing.
Question 4 True / False
Using a single flat 10-to-1024 decoder for a 10-bit address requires fewer output wires than 2D decoding with the same address width.
TTrue
FFalse
Answer: False
A flat 10-to-1024 decoder requires 1,024 output lines. 2D decoding splits the address 5+5, requiring a 5-to-32 row decoder (32 outputs) plus a 5-to-32 column decoder (32 outputs) = 64 lines total. 64 is far fewer than 1,024. This reduction — from 2^n to 2 × 2^(n/2) — is the primary motivation for 2D decoding in memory design.
Question 5 Short Answer
Why does 2D address decoding reduce hardware complexity compared to a flat decoder, and what is the tradeoff introduced?
Think about your answer, then reveal below.
Model answer: 2D decoding splits the n-bit address into two halves, each decoded independently. This reduces output lines from 2^n to 2 × 2^(n/2) — a massive saving for wide addresses. The tradeoff is that memory selection now requires two signals (row and column) that must both be asserted to select a cell, introducing a two-phase access sequence rather than a single decode step. This adds slight timing complexity but is vastly cheaper in hardware.
The exponential-to-linear reduction in decoder outputs is what makes large memory arrays feasible. A 32-bit flat decoder would need 4 billion output lines — physically impossible. 2D decoding with 16-bit halves needs only 2 × 65,536 = 131,072 lines. Hierarchical decoding extends this further by cascading multiple levels, each operating on a subset of address bits.