Questions: Memory Bus Architecture and Interconnect

Question 1

Two devices attempt to transmit data on a shared bus at exactly the same time, with no arbitration mechanism in place. What is the most likely outcome?

• A. Both writes succeed, with the later one overwriting the first
• B. The bus becomes corrupted as conflicting voltages are driven on the same wires simultaneously
• C. The CPU automatically prioritizes its own request over the other device
• D. The system pauses until both devices are ready, then combines the data

Answer: (B)

Without arbitration, two devices driving the bus simultaneously force conflicting electrical voltages onto the same wires. The result is a corrupted signal that neither device intended — not a prioritization or a merge. This is why arbitration is not optional: it is required for the bus to function as a reliable shared medium at all. Option A imagines the bus as having memory or sequencing logic it does not have.

Question 2

A system designer is choosing between a wider 64-bit data bus and a narrower 32-bit data bus running at the same clock frequency. Widening the bus to 64 bits primarily improves:

• A. Clock frequency, allowing more bus cycles per second
• B. Throughput, by transferring twice as many bytes per bus cycle
• C. Arbitration fairness, since more bits reduce the chance of contention
• D. Latency, since each individual transfer completes in fewer cycles

Answer: (B)

Bus width directly controls how many bytes are transferred in a single bus cycle — doubling the width doubles the data moved per cycle, which doubles peak throughput. It does not change the clock frequency, which is a separate design parameter. It also doesn't directly reduce latency (the time to complete one transfer) or affect arbitration fairness, which is a protocol-level concern independent of bus width.

Question 3

Widening a data bus from 32 to 64 bits doubles the bus clock frequency.

• T. True
• F. False

Answer: False

False. Bus width and clock frequency are independent parameters. Widening the data bus increases how much data is transferred per clock cycle (throughput), not how many cycles occur per second (frequency). A 64-bit bus at 100 MHz transfers twice as much data per cycle as a 32-bit bus at 100 MHz, but both run at the same clock rate.

Question 4

Bus arbitration is necessary because multiple devices sharing a bus may try to use it at the same time, and driving conflicting signals simultaneously would corrupt data.

• T. True
• F. False

Answer: True

True. A shared bus has a single set of wires that all connected devices can drive. Without arbitration, simultaneous access creates electrical conflicts — two devices outputting different voltages on the same wire produce an undefined result. Arbitration is the mechanism that prevents this by granting bus access to only one device at a time.

Question 5

Why have modern computer systems moved away from a single shared bus toward point-to-point interconnects and crossbar switches?

Model answer: A single shared bus is a bottleneck: only one transfer can happen at a time, so all devices contend for the same resource. As the number of connected components and their speed requirements grew, a single bus could no longer provide adequate bandwidth. Point-to-point interconnects give each pair of components a dedicated link, allowing multiple transfers to occur simultaneously without contention. Crossbar switches extend this by routing any source to any destination simultaneously, eliminating the serialization inherent in a shared bus.

The key limitation of shared-bus architectures is that throughput is capped at one transfer per bus cycle regardless of how many devices are connected. Point-to-point designs like PCIe and AXI-based NoCs scale bandwidth with the number of active connections, which is why they dominate in high-performance designs — while the core concepts of address/data/control signals and protocol handshaking remain unchanged.