Questions: Memory Interleaving and Bandwidth Optimization

Question 1

A program accesses memory addresses 0, 4, 8, 12, and 16 in sequence using a 4-way low-order interleaved system where the 2 low-order address bits select the bank. What happens to memory bandwidth?

• A. The accesses are distributed evenly across all four banks, achieving 4× bandwidth
• B. All accesses hit bank 0, creating bank conflicts and eliminating the parallelism
• C. The memory controller automatically detects the stride and redistributes the accesses
• D. Two banks are accessed in parallel, achieving 2× bandwidth

Answer: (B)

With 4-way low-order interleaving, bank = address mod 4. Addresses 0, 4, 8, 12, 16 all give remainder 0, so every access goes to bank 0. This stride-4 access pattern — exactly the width of the interleaving — creates a bank conflict on every access and collapses parallelism to single-bank throughput. Sequential access (0, 1, 2, 3, 4, ...) would distribute across all four banks and achieve the full 4× benefit.

Question 2

Why does low-order interleaving improve bandwidth for sequential access but not for a stride-N access pattern (where N equals the number of banks)?

• A. Low-order interleaving only works when the CPU cache is disabled
• B. Sequential access hits a different bank each cycle; stride-N access hits the same bank every time, serializing requests
• C. Stride-N accesses are too large for the memory address space
• D. Low-order interleaving was designed only for instruction fetch, not data access

Answer: (B)

The bank assignment is address mod N. Sequential addresses (0, 1, 2, 3, ...) produce consecutive bank indices (0, 1, 2, 3, 0, 1, ...), spreading load and enabling parallelism. A stride-N pattern (0, N, 2N, 3N, ...) always maps to bank 0, leaving the other N−1 banks idle. The benefit of interleaving is entirely determined by whether the access pattern actually uses different banks — hardware cannot compensate for a pathological stride.

Question 3

In low-order memory interleaving, consecutive memory addresses are placed in the same bank to improve locality of reference.

• T. True
• F. False

Answer: False

This describes high-order interleaving, not low-order. In low-order interleaving, the least significant address bits select the bank, which means consecutive addresses map to consecutive banks (0, 1, 2, 3, 0, 1, ...). This is the property that enables parallel access for sequential patterns. High-order interleaving uses the most significant bits, placing large contiguous blocks in the same bank — useful for reducing inter-bank contention in multiprocessor systems, but providing no bandwidth improvement for sequential single-processor access.

Question 4

N-way memory interleaving can achieve up to N times the memory bandwidth of a single-bank system when access patterns spread requests across all N banks.

• T. True
• F. False

Answer: True

This is the design goal of interleaving. When N successive requests each go to a different bank, all N banks can be working simultaneously, pipelining their access cycles. The first bank finishes and delivers data while banks 2 through N are still working — so one result arrives every cycle instead of one result every full access cycle. The N× improvement is the ideal maximum, achieved only when every access hits a different bank.

Question 5

Why does the benefit of N-way memory interleaving depend on the access pattern rather than just the number of banks?

Model answer: Interleaving distributes consecutive addresses across banks so parallel accesses can overlap. If the access pattern spreads requests to different banks, all N banks work simultaneously. If the pattern repeatedly hits the same bank (a bank conflict), each access must wait for the previous one to complete — the parallelism collapses entirely. The hardware can only exploit the N banks if the software's memory access pattern actually uses them.

The key insight is that N-way interleaving is a potential, not a guarantee. The memory system provides the parallel infrastructure; whether it's utilized depends entirely on whether successive addresses happen to fall in different banks. This is why access patterns — sequential, random, strided — matter so much in memory system design, and why compiler and hardware architects think carefully about array layout and prefetching.