Questions: MOSFET Fundamentals

Question 1

A MOSFET is operating in saturation. Which variable primarily controls the drain current I_D in this region?

• A. V_DS, the drain-to-source voltage
• B. V_GS − V_T, the gate overdrive voltage
• C. The channel resistance, which depends on V_DS
• D. The gate current I_G flowing through the oxide

Answer: (B)

In saturation (V_DS ≥ V_GS − V_T), the drain current is I_D = (k_n/2)(V_GS − V_T)² and is nearly independent of V_DS. The current is controlled by the gate overdrive voltage (V_GS − V_T), not by V_DS. This makes the MOSFET behave like a voltage-controlled current source in saturation — the gate voltage sets the current, and the drain-source voltage simply maintains the saturation condition. This is why saturation is the amplifier region: small changes in V_GS produce predictable changes in I_D regardless of what's happening at the drain.

Question 2

A digital designer claims that a CMOS inverter wastes significant power even when its output is held static (not switching). Is this correct?

• A. Yes — both NMOS and PMOS are always partially on, creating a constant current path from V_DD to ground
• B. No — in steady state, one transistor is fully on and the other is fully off, so there is no DC path from V_DD to ground
• C. Yes — the gate capacitance of the transistors continuously draws current from the supply
• D. No — CMOS logic does not use transistors in steady state; it only activates them during switching

Answer: (B)

In a CMOS inverter at steady state, NMOS and PMOS are designed to be complementary: when the input is high, NMOS is on and PMOS is off; when the input is low, PMOS is on and NMOS is off. In either case, one transistor is in cutoff (essentially an open circuit), so no DC current path exists from V_DD to ground. Power is only dissipated during switching transitions, when both transistors may be partially on momentarily, and when charging/discharging load capacitance. This negligible static power dissipation is the fundamental reason CMOS enables billions of transistors on a chip — if every transistor drew DC current, the chip would instantly overheat.

Question 3

When a MOSFET enters saturation (V_DS ≥ V_GS − V_T), it behaves like a BJT in saturation: both devices are fully switched on and act as low-resistance paths.

• T. True
• F. False

Answer: False

This is the most dangerous naming confusion in transistor circuits. MOSFET saturation and BJT saturation are entirely different operating regimes. MOSFET saturation is the *amplifier* region, where the channel is pinched off at the drain end and I_D depends on V_GS but not V_DS — the device acts as a voltage-controlled current source. BJT saturation is the *switch-fully-on* region, where both junctions are forward biased and V_CE is very small. The MOSFET equivalent of 'BJT saturation' is the *triode (linear) region*, where V_DS is small and the device acts as a voltage-controlled resistor. The terms were chosen independently and unfortunately share the word 'saturation' for opposite reasons.

Question 4

The gate of a MOSFET draws essentially no DC current because an insulating oxide layer physically separates the gate terminal from the semiconductor channel.

• T. True
• F. False

Answer: True

This is the MOSFET's defining structural advantage over the BJT. The gate is formed from a conductor (metal or polysilicon) separated from the semiconductor channel by a thin layer of silicon dioxide (SiO₂), which is an excellent insulator. Because there is no DC conduction path between the gate and the channel, gate current is essentially zero at DC. The input impedance looking into the gate is effectively infinite at low frequencies — orders of magnitude higher than a BJT base. This means MOSFET gates draw negligible power from the driving circuit and can control large drain currents with virtually no input current, a critical advantage for digital logic density.

Question 5

Why does CMOS logic consume negligible static power, and why does this matter for modern integrated circuit design?

Model answer: CMOS uses complementary NMOS and PMOS transistors wired so that exactly one is off (in cutoff, drawing no current) in every static logic state. When the input is high, NMOS conducts and PMOS is off; when the input is low, PMOS conducts and NMOS is off. In either case, the off transistor presents a near-open circuit between V_DD and ground, so no static current flows and no static power is dissipated. Power is consumed only during switching transitions (charging/discharging gate capacitances) and briefly when both transistors are simultaneously partially on. This matters enormously for chip design: a chip with a billion transistors all drawing even 1 μA each would dissipate 1,000 watts at idle. CMOS's near-zero static dissipation is what makes dense, battery-powered computing physically possible.

As transistor feature sizes have shrunk, leakage currents through the oxide have increased, making static power dissipation a growing concern in modern CMOS — one of the major challenges for the semiconductor industry below 10 nm. But the fundamental CMOS principle of complementary switching remains the basis of essentially all digital logic, from microcontrollers to server chips.