Questions: Multi-Cycle Processor Design and Execution States

Question 1

A multi-cycle processor is designed to run at a faster clock than a single-cycle processor. How is this possible if some instructions now require more total cycles to complete?

• A. Multi-cycle processors use a superscalar architecture that executes multiple instructions simultaneously
• B. The clock period is set by the longest single phase, not the longest full instruction, so shorter phases allow a faster clock
• C. The processor skips unnecessary phases for simple instructions, reducing total cycle count
• D. Intermediate registers speed up data transfer between functional units

Answer: (B)

In single-cycle design, the clock period must accommodate the slowest instruction end-to-end (e.g., a memory load through the ALU and back). Multi-cycle breaks execution into phases; the clock only needs to be long enough for the longest *single phase*. This allows a much faster clock. Individual instruction latency (in cycles) may increase, but the faster clock can reduce total execution time for the overall mix of instructions.

Question 2

Why does a multi-cycle processor require intermediate registers between stages, while a single-cycle design does not?

• A. Multi-cycle processors have more functional units that must communicate simultaneously
• B. Intermediate registers act as a cache to speed up repeated instruction fetches
• C. Each stage occupies a separate clock cycle, so results computed in one cycle must be stored for the next cycle to use
• D. The finite state machine controller requires register storage to track its current state

Answer: (C)

In single-cycle design, all signals propagate combinationally within one clock period — values persist long enough for subsequent stages. In multi-cycle, each stage occupies a separate clock cycle. Once the clock ticks, combinational outputs vanish. Intermediate registers (instruction register, ALU output register, etc.) are required to hold partial results across clock boundaries so later stages can use them.

Question 3

Different instruction types complete in different numbers of clock cycles in a multi-cycle processor.

• T. True
• F. False

Answer: True

This is the defining property of multi-cycle design. An R-type instruction might use 4 cycles (skipping memory access), a load uses all 5, and a branch might need only 3. The FSM controller selects the correct sequence of states per instruction type. This is the efficiency advantage over single-cycle, where every instruction must wait out the full period regardless of what it actually needs.

Question 4

A multi-cycle processor typically executes programs faster than a single-cycle processor because it uses a shorter clock period.

• T. True
• F. False

Answer: False

While the multi-cycle design uses a shorter clock period, individual instructions take more cycles to complete. Whether programs run faster overall depends on the instruction mix, the relative clock speedup, and the implementation. The real value of multi-cycle design is conceptual: it decomposes execution into discrete stages — the same stages pipelining overlaps — making the leap to pipelining natural.

Question 5

Why is multi-cycle processor design described as a critical stepping stone to pipelining, and what specifically makes the transition to pipelining natural once you understand multi-cycle?

Model answer: Multi-cycle already decomposes execution into discrete stages (fetch, decode, execute, memory, writeback) and places intermediate registers between them. Pipelining takes these same stages and overlaps them — while instruction N is in decode, instruction N+1 enters fetch. The stage boundaries and inter-stage registers already exist in the multi-cycle design. The only difference is that multi-cycle runs one instruction through all stages sequentially, while pipelining fills all stages simultaneously.

The conceptual shift from multi-cycle to pipelining is: instead of waiting for stage 1 to be idle before the next instruction uses it, pipelining starts the next instruction in stage 1 the moment the current instruction advances to stage 2. The hardware is nearly identical — the same stage registers, control logic, and functional units are reused. Understanding multi-cycle makes this insight feel obvious rather than mysterious.