Questions: Multilevel Cache Design and Coordination

5 questions to test your understanding

Score: 0 / 5
Question 1 Multiple Choice

A multicore processor uses an inclusive L3 cache. Core A wants to modify a cache line that Core B might have cached. Why does the inclusive design simplify this coherence check?

AInclusive caches use hardware locks that serialize all cache accesses across cores
BBecause every L1 and L2 cache line is guaranteed to exist in L3, the coherence protocol only needs to probe L3 — if the line isn't there, it isn't anywhere
CInclusive caches are smaller and faster to search than exclusive caches
DThe shared L3 directly controls all L1 and L2 caches, so it can invalidate them without probing
Question 2 Multiple Choice

Which workload scenario best illustrates the performance advantage of an exclusive cache hierarchy over an inclusive one?

AMultiple cores frequently sharing the same hot data, requiring rapid cross-core coherence checks
BEach core accessing a distinct, large private dataset where L2 misses rarely repeat, so avoiding duplicated data across levels maximizes total effective capacity
CA workload requiring very frequent L1 hits, where L3 behavior is largely irrelevant
DA single-threaded workload with a working set that fits entirely within L1
Question 3 True / False

In an inclusive cache hierarchy, every cache line present in an L1 cache is also guaranteed to be present in L2 and L3.

TTrue
FFalse
Question 4 True / False

A program whose entire working set fits within the L2 cache will run significantly faster on a processor with a larger L3 cache.

TTrue
FFalse
Question 5 Short Answer

Explain why an exclusive cache hierarchy achieves greater total effective capacity than an inclusive one with the same physical cache sizes, and what tradeoff this introduces.

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