In 8-bit two's complement, you add 80 + 60. The result is −116 and the carry-out bit from the MSB is 0. Which of the following best describes what happened?
ANo error occurred — the carry-out being 0 means the result is correct
BOverflow occurred because two positive numbers produced a negative result
CUnderflow occurred because the result is negative
DOverflow cannot occur with positive numbers, so this must be a hardware bug
The detection rule for two's complement overflow is not about the carry-out bit alone — it is about whether two operands of the same sign produced a result of the opposite sign. 80 + 60 = 140, which exceeds the 8-bit range of −128 to +127. Both inputs are positive, but the result wrapped to −116 (negative), proving overflow. Option A confuses carry-out with overflow; carry-out is one input to the overflow detection logic but is not sufficient on its own.
Question 2 Multiple Choice
Which of the following additions in two's complement arithmetic can never produce an overflow, regardless of the operand values?
AAdding two large positive numbers
BAdding two large negative numbers
CAdding a positive number and a negative number
DAdding any number to zero
When adding a positive and a negative number in two's complement, the result always lies between the two operands in magnitude, so it always fits within the representable range — overflow cannot occur. By contrast, adding two positive numbers can overflow into the negative range, and adding two negative numbers can overflow into the positive range. The sign-matching rule ('same-sign inputs → overflow possible; opposite-sign inputs → overflow impossible') encodes this insight directly.
Question 3 True / False
In 8-bit two's complement, adding 100 + 50 produces −106. This is an overflow, and the hardware can detect it by observing that two positive inputs produced a negative output.
TTrue
FFalse
Answer: True
This is exactly the two's complement overflow detection rule. 100 + 50 = 150, which exceeds +127, the maximum 8-bit representable value. The result wraps to −106. The sign-check rule — both inputs are positive but the output is negative — is both necessary and sufficient to detect overflow in two's complement addition.
Question 4 True / False
If the carry-out bit from the most significant bit position is 1 after an addition, an overflow has definitely occurred.
TTrue
FFalse
Answer: False
This is a common misconception. In two's complement arithmetic, overflow is detected by comparing the carry INTO the MSB with the carry OUT of the MSB — overflow occurs only when these two carry bits differ. A carry-out of 1 can occur with no overflow (e.g., adding a positive and a large negative number may produce a carry-out without violating the representable range). Conversely, overflow can occur with a carry-out of 0 (e.g., two large positive numbers). The carry-out alone is not the overflow indicator.
Question 5 Short Answer
Explain why adding a positive number and a negative number in two's complement can never produce an overflow.
Think about your answer, then reveal below.
Model answer: Because the result must lie between the two operands in magnitude. Adding a positive and a negative number moves the sum toward zero from both sides — the result is always smaller in absolute value than the larger operand. Since both operands are representable, and the result is bounded by the larger, it is always within the representable range.
The intuition is geometric: a positive and negative number pull in opposite directions on the number line, so the sum is always between them and cannot escape the bounds. This is why the sign-matching rule works: you only need to worry about two inputs that both push in the same direction — two positives can exceed the positive maximum, and two negatives can fall below the negative minimum. Opposite-sign inputs self-constrain.