A pipeline has full data forwarding (bypassing) implemented. Consider the instruction sequence: LOAD R1, [addr]; ADD R2, R1, R3. How many stall cycles are required between these two instructions?
AZero — data forwarding eliminates all data hazard stalls
BOne — a load-use hazard requires one stall even with full forwarding
CTwo — the loaded value is not available until write-back, two stages after execute
DThree — the pipeline must wait until LOAD completes all five stages
This is the load-use hazard — the one case where data forwarding cannot eliminate the stall. In a standard 5-stage pipeline, data forwarding routes the result from the end of the execute stage directly to the next instruction's execute input. But a LOAD instruction doesn't have the data until the end of the memory access stage (one stage later than execute). Since ADD needs R1 at its execute stage, which begins one cycle after LOAD's memory stage ends, there is exactly one cycle where the data simply is not available yet. One stall is inserted. The misconception that 'forwarding eliminates all stalls' is the most common error in pipeline hazard analysis.
Question 2 Multiple Choice
A branch instruction is in the pipeline and the branch predictor predicts 'not taken.' Three instructions after the branch have already been fetched speculatively. The branch turns out to be taken. What happens?
AThe processor raises an exception and restarts from the branch
BThe three speculatively fetched instructions are flushed, and the pipeline restarts from the branch target
CThe processor stalls until the branch condition is evaluated before fetching any further instructions
DThe three instructions complete execution but their results are discarded
A branch misprediction causes the pipeline to flush the incorrectly fetched instructions (converting them to bubbles/NOPs) and restart fetching from the correct branch target address. This is not an exception — it is a normal, expected event handled by the pipeline's branch misprediction recovery mechanism. The misprediction penalty is typically 2-3 cycles in a simple pipeline (the number of cycles between branch fetch and when the branch resolves). Critically, the speculatively fetched instructions must be flushed before completing — allowing them to execute would compute wrong results.
Question 3 True / False
Data forwarding (bypassing) eliminates the need for stall cycles in most data hazard cases.
TTrue
FFalse
Answer: False
False. Data forwarding eliminates stalls for most data hazards — for example, the result of an ADD in the execute stage can be forwarded directly to the next instruction's execute stage, eliminating a 2-cycle stall. But the load-use hazard cannot be solved by forwarding alone. A LOAD instruction's result is only available after the memory access stage, which is one cycle too late to forward directly to the immediately following instruction's execute stage. One stall cycle must still be inserted. This is a common misconception: forwarding is powerful but not a complete solution.
Question 4 True / False
Branch mispredictions are processor errors that indicate a bug in branch prediction logic; a correctly functioning processor should rarely mispredict a branch.
TTrue
FFalse
Answer: False
False. Branch mispredictions are expected, normal events in any processor with speculative execution. A predictor achieving 95%+ accuracy still mispredicts millions of branches per second in a modern processor running at GHz speeds. A misprediction means the predicted outcome was wrong — not that the hardware malfunctioned. The pipeline is designed to handle mispredictions gracefully by flushing incorrect instructions and restarting from the correct path. Mispredictions cause performance penalties (wasted cycles), not incorrect computation, because the incorrect instructions are flushed before they can commit results.
Question 5 Short Answer
Why does a load-use hazard require a stall cycle even when the pipeline has full data forwarding, while a RAW (read-after-write) hazard between two arithmetic instructions does not?
Think about your answer, then reveal below.
Model answer: In a 5-stage pipeline, arithmetic instructions produce their result at the end of the execute (EX) stage. Data forwarding routes this result directly back to the beginning of the next instruction's EX stage, so consecutive arithmetic instructions can run without stalls. A LOAD instruction, however, doesn't have the data until the end of the memory access (MEM) stage — one full stage later than EX. If the instruction immediately after the load needs that value, it enters its EX stage before the load has even completed MEM. There is no way to forward data that hasn't been retrieved yet; the pipeline must insert one bubble to let the load complete MEM before the dependent instruction begins EX.
The root cause is the pipeline stage at which data becomes available: EX for arithmetic, MEM for loads. Forwarding can only move data forward in time within the pipeline — it cannot make data available before it is physically computed or retrieved from memory. This one-cycle gap between when a load produces data and when the next instruction needs it is structurally unavoidable without deeper pipeline restructuring or out-of-order execution.