Questions: Shift Register Design and Applications

Question 1

A UART receiver must accept 8 bits arriving one per clock cycle on a serial line and then deliver all 8 bits at once to the processor. Which shift register configuration does this?

• A. Parallel-In, Serial-Out (PISO) — loads all 8 bits at once and shifts them out
• B. Serial-In, Parallel-Out (SIPO) — shifts in one bit per clock, then outputs all in parallel
• C. Serial-In, Serial-Out (SISO) — creates a delay line equal to 8 clock cycles
• D. Parallel-In, Parallel-Out (PIPO) — stores and re-outputs all 8 bits simultaneously

Answer: (B)

SIPO is exactly the serial-to-parallel converter a UART receiver needs: each incoming bit shifts into the register on successive clock edges, and after 8 clocks the full byte appears simultaneously on the parallel output lines. PISO does the opposite conversion (parallel byte → serial stream) and is used by the UART transmitter. SISO just delays data; PIPO is a storage register.

Question 2

A 4-bit register holds the value 0011 (decimal 3). After shifting left by 2 positions, what value does it hold, and why?

• A. 1100 (decimal 12), because shifting left by N positions multiplies by 2^N
• B. 0110 (decimal 6), because shifting left adds the original value to itself once
• C. 1001 (decimal 9), because the bits rotate rather than shift
• D. 0011 (decimal 3), because the shift only moves the bits temporarily

Answer: (A)

Shifting left by N positions is equivalent to multiplying by 2^N. Shifting 0011 left by 2 gives 1100, which is 3 × 4 = 12. This works because each left shift moves each bit to a position with twice the place value. Note that bit overflow is possible — here the two leading zeros absorb the shift safely. This arithmetic property is why shift registers can replace multiplier circuits for multiplication by powers of two.

Question 3

A shift register with N flip-flops takes exactly N clock cycles to move a bit from the input to the last (Nth) output stage.

• T. True
• F. False

Answer: True

Each clock edge shifts every bit one position forward — one flip-flop to the next. A bit enters at position 1 and must traverse all N stages, so it takes exactly N clock cycles to reach the Nth output. This is the defining behavior of a SISO (shift-through) configuration and explains why shift registers can be used as programmable delay lines.

Question 4

A PISO (Parallel-In, Serial-Out) shift register is the configuration used to convert incoming serial data into a parallel byte for a processor to read.

• T. True
• F. False

Answer: False

PISO does the opposite: it accepts all bits in parallel (e.g., a byte from a processor) and outputs them one bit at a time on a serial line. It is used by a UART transmitter. The configuration that converts serial input to parallel output — what a UART receiver needs — is SIPO (Serial-In, Parallel-Out). Confusing these is the most common mistake with shift register configurations.

Question 5

Why is shifting a binary number one position to the left equivalent to multiplying it by 2?

Model answer: In binary positional notation, each bit position represents a power of 2: the rightmost bit is 2^0 = 1, the next is 2^1 = 2, then 2^2 = 4, etc. When you shift every bit one position left, each bit moves to a position whose place value is exactly double its previous place value. A bit worth 2^k becomes worth 2^(k+1) = 2 × 2^k. Since this doubling applies to every bit simultaneously, the total value of the number doubles.

This is the hardware basis for fast power-of-2 arithmetic. A shift operation takes one clock cycle regardless of word width, whereas a general multiplier circuit requires many more gates and cycles. Compilers exploit this: when you write x * 4 in C, the compiler often emits a left-shift-by-2 instruction rather than a multiply, because the processor can execute it faster.