Questions: Static RAM (SRAM) Cell Design and Arrays

Question 1

A chip designer needs to implement 16 GB of main memory for a laptop. Should they use SRAM or DRAM?

• A. SRAM, because it does not require refresh and is therefore more power-efficient at large scales
• B. DRAM, because SRAM's six-transistor cell makes 16 GB impractical to fit on a chip
• C. SRAM, because single-cycle access is required for all memory in modern processors
• D. Either works equally well; the choice depends only on desired clock speed

Answer: (B)

SRAM uses six transistors per bit versus DRAM's one transistor and one capacitor. This 6× area penalty makes SRAM economically impractical for gigabyte-scale storage. Option A is the most tempting wrong answer — SRAM does avoid the power cost of refresh, but its standby power from the always-active inverters and its massive area cost make it unsuitable for main memory. DRAM's density advantage defines its role at the bottom of the memory hierarchy.

Question 2

During an SRAM read, what physically happens that distinguishes it from a DRAM read?

• A. The stored capacitor charge is sensed and then immediately refreshed to prevent data loss
• B. Both bit lines are precharged high; the cross-coupled inverters pull one side slightly lower, and a sense amplifier amplifies the difference
• C. The access transistors discharge the stored bit into the bit line, which must then be rewritten
• D. The cross-coupled inverters are temporarily disabled to allow non-destructive voltage measurement

Answer: (B)

SRAM reads are non-destructive because the cross-coupled inverters actively maintain the stored value. Precharging both bit lines and letting the inverters create a small differential, then amplifying it, gives a fast single-cycle result without disturbing the cell. Options A and C describe the DRAM read cycle, which is destructive — the capacitor discharges during reading and must be refreshed. Option D is nonsensical; disabling the inverters would destroy the stored state.

Question 3

SRAM cells retain their stored value indefinitely without periodic refresh because the cross-coupled inverters actively regenerate the bit as long as power is supplied.

• T. True
• F. False

Answer: True

This is exactly right. The two cross-coupled inverters form a feedback loop: each inverter's output drives the other's input, locking in either a 0 or 1. As long as power is present, this feedback continuously reinforces the stored value. DRAM, by contrast, stores charge on a capacitor that leaks over time, requiring periodic refresh cycles to restore the charge before it drops below a detectable threshold.

Question 4

SRAM is commonly used for main memory in modern computers because its lack of refresh overhead makes it practical for large storage capacities.

• T. True
• F. False

Answer: False

This reverses the actual tradeoff. SRAM is never used for main memory because six transistors per bit consumes far too much silicon area compared to DRAM's one-transistor-one-capacitor cell. SRAM's speed and no-refresh advantages make it ideal for small, fast structures — register files and L1/L2/L3 caches — where kilobytes to megabytes are needed at single-cycle access speeds. Main memory (gigabytes) uses DRAM despite its slower access and refresh overhead.

Question 5

Why does SRAM use six transistors per bit rather than a simpler design like DRAM's one-transistor-one-capacitor cell, and what consequence does this have for where SRAM appears in the memory hierarchy?

Model answer: SRAM needs six transistors to implement cross-coupled inverters (four transistors) plus two access transistors. This feedback loop is what makes SRAM fast and self-maintaining — but it costs 6× the silicon area of a DRAM cell. The consequence is that SRAM is economically viable only for small, high-speed structures: register files (tens to hundreds of entries read every cycle) and cache memory (kilobytes to megabytes bridging CPU and main memory). DRAM's density advantage makes it the only practical choice for gigabyte-scale main memory despite its slower access and refresh requirements.

The six-transistor design is not over-engineering — each transistor serves a purpose. Four form the inverter pair that maintains state through feedback; two are access gates controlled by the word line. Simpler latch designs are noisier and less robust to process variation. The 6T cell is essentially the minimum reliable design for a single-bit storage element. This area cost directly determines SRAM's role: fast but small at the top of the hierarchy (caches, registers), with DRAM's density taking over for the bulk of memory.