A control engineer wants zero steady-state error tracking a constant step input. She has a stable Type 0 system with gain K = 10. She increases gain to K = 10,000. What happens to the steady-state error?
AIt becomes exactly zero — very high gain forces the system to track perfectly
BIt decreases substantially but remains a small positive nonzero value
CIt stays unchanged because gain has no effect on steady-state error
DIt becomes negative because the system permanently overshoots the reference
For a Type 0 system, ess = R/(1+Kp) where Kp = lim[s→0] G(s), which equals K times other finite terms. Increasing K raises Kp, which reduces ess — but ess = R/(1+Kp) approaches zero only as Kp → ∞. At any finite K, Kp is finite and ess is a small but nonzero value. To achieve exactly zero steady-state error to a step, you need at least one integrator in the open-loop path (Type 1 system). No amount of finite gain can substitute for the structural property of having an integrator. High gain reduces error; system type determines whether error can reach zero.
Question 2 Multiple Choice
A stable Type 1 system has velocity error constant Kv = 4 and is tracking a ramp input with slope R = 12 units/sec. What is the steady-state tracking error?
A0, because a Type 1 system tracks all polynomial inputs without error
B12 units, because the error equals the ramp slope for any Type 1 system
C3 units, computed as ess = R/Kv = 12/4
DCannot be determined without knowing the closed-loop pole locations
A Type 1 system tracks step inputs with zero error (because one integrator makes G(0) → ∞), but it has finite steady-state error to a ramp input, given by ess = R/Kv. With R = 12 and Kv = 4, ess = 3. Option A is the critical misconception: Type 1 eliminates step error but NOT ramp error — you need Type 2 (two integrators) for zero ramp tracking error. The hierarchy is exact: each system type eliminates steady-state error to one more class of polynomial input, but not to the next.
Question 3 True / False
A stable Type 2 control system will track both step and ramp reference inputs with zero steady-state error.
TTrue
FFalse
Answer: True
A Type 2 system has two integrators in the open-loop forward path. Each integrator contributes a factor of 1/s to G(s), and together they make G(s) → ∞ faster than s² as s → 0. Applying the final value theorem to E(s) = R(s)/(1+G(s)) for both a step (R(s) = 1/s) and a ramp (R(s) = 1/s²) yields ess = 0 in both cases. However, two integrators contribute −180° of cumulative phase lag, making stability analysis critical — zero steady-state error is achieved at the cost of substantially reduced phase margin.
Question 4 True / False
Adding an integrator to the open-loop forward path increases system type and reduces steady-state error without affecting the system's stability.
TTrue
FFalse
Answer: False
Each integrator contributes −90° of phase lag at all frequencies, directly eroding the phase margin that measures stability robustness. A system with 60° of phase margin may become marginally stable or oscillatory after adding an integrator without compensating for the phase loss. This is the fundamental tension in control design: integrators reduce steady-state error but threaten stability. This is precisely why PID controllers include a derivative term — to add phase lead that compensates for the phase lag introduced by the integral term.
Question 5 Short Answer
Explain why system type — the number of integrators in the open-loop path — rather than loop gain determines whether a control system can achieve exactly zero steady-state error to a given class of input.
Think about your answer, then reveal below.
Model answer: System type determines the structural ability to eliminate steady-state error because each integrator contributes a factor of 1/s to G(s), making G(s) → ∞ as s → 0. The closed-loop steady-state error is ess = lim[s→0] s·R(s)/(1+G(s)). For this limit to reach zero, G(0) must be infinite — and only an integrator (a pole at the origin) achieves that. Loop gain K scales G(s) by a finite constant: it can make G(0) very large for a Type 0 system, making ess very small, but ess = R/(1+K·finite) never reaches exactly zero for finite K. An integrator makes the denominator literally infinite at DC, forcing ess = 0. You cannot substitute quantity of gain for the qualitative structural property of having a pole at the origin.
This distinction between 'reduces error' and 'eliminates error' is the insight that separates genuine understanding from surface familiarity with the formulas. Students who confuse high gain with system type will make design errors — thinking they've solved a tracking problem with gain when only an integrator can actually solve it.