Questions: Steady-State Error: System Type and Error Constants

Question 1

A Type 0 closed-loop position control system is given a step (constant position) command. What is its steady-state response?

• A. The output reaches and holds the commanded position with zero steady-state error
• B. The output approaches the commanded position but maintains a finite, nonzero steady-state error
• C. The output falls increasingly far behind the command over time, with error growing without bound
• D. The output oscillates indefinitely around the commanded position without settling

Answer: (B)

A Type 0 system has no open-loop integrators and tracks a step with a finite steady-state error given by SSE = 1/(1 + Kp), where Kp is the position error constant. It cannot achieve zero SSE to a step — that requires at least one integrator (Type 1 or higher). Option C describes the response of any system to an input one order higher than it can track (e.g., a Type 0 system to a ramp). Option A would require Type 1 or above.

Question 2

An engineer needs to track a ramp input with zero steady-state error. She considers two options: (a) increasing the gain of a Type 0 system, or (b) adding one integrator to the forward path to make it Type 1. Which approach actually achieves zero SSE to a ramp?

• A. Either option — sufficiently high gain in a Type 0 system can drive ramp error to zero
• B. Option (a) only — gain can always be increased to eliminate steady-state error to any input
• C. Option (b) only — only a Type 1 or higher system can track a ramp with zero steady-state error
• D. Neither — ramp tracking with zero SSE requires at least a Type 2 system

Answer: (C)

For a ramp input, SSE = 1/Kv, where Kv = lim(s→0) s·G(s). In a Type 0 system, G(s) has no poles at s=0, so s·G(s) → 0 as s→0, meaning Kv = 0 and SSE = 1/0 = ∞ regardless of gain. Increasing gain does not change the system type — it cannot turn an infinite error finite. Adding one integrator creates a Type 1 system with Kv = finite, giving SSE = 1/Kv. Increasing the gain of a Type 1 system reduces this finite error but only another integrator (Type 2) eliminates it entirely.

Question 3

A Type 1 system tracks a constant position (step) command with zero steady-state error and tracks a constant velocity (ramp) command with a finite steady-state error.

• T. True
• F. False

Answer: True

System type N guarantees zero SSE to all polynomial inputs of degree less than N, and finite SSE to the Nth-degree input. A Type 1 system (N=1) achieves zero error to a step (degree 0) and finite error to a ramp (degree 1), characterized by the velocity error constant Kv = lim(s→0) s·G(s), with SSE = 1/Kv. A parabolic (degree 2) input produces infinite error for a Type 1 system. This hierarchy is the central result of system type analysis.

Question 4

Increasing loop gain is typically sufficient to eliminate steady-state error for any input, regardless of system type.

• T. True
• F. False

Answer: False

Gain can reduce finite steady-state errors but cannot eliminate them or convert infinite errors to finite ones. For a Type 0 system tracking a step, SSE = 1/(1+Kp), and Kp grows with gain — so high gain reduces SSE toward zero but never reaches it. For a Type 0 system tracking a ramp, SSE is infinite regardless of gain because the system lacks the integrating action needed to follow a moving reference. Only adding an integrator (increasing system type) can eliminate an SSE class entirely.

Question 5

A Type 1 system tracks a step with zero error and a ramp with finite error. Why does adding a second integrator (making it Type 2) help with ramp tracking — and what is the cost?

Model answer: A Type 2 system has two open-loop integrators. For a ramp input, the velocity error constant Kv = lim(s→0) s·G(s) becomes infinite (since G(s) has two poles at s=0, s·G(s) → ∞), giving SSE = 1/Kv = 0. The Type 2 system can also track a parabolic (acceleration) input with finite error. The cost is stability: each integrator adds 90° of phase lag to the open-loop transfer function, reducing the phase margin. A Type 2 system is harder to stabilize and requires careful compensator design — more integrators means the loop is closer to instability.

This tradeoff is the central tension in steady-state error vs. stability design. Adding integrators improves tracking accuracy but erodes phase margin, potentially causing oscillations or instability. Compensation design (lead, lag, PID) exists precisely to manage this tradeoff: lag compensation adds low-frequency gain to reduce SSE without moving the gain crossover frequency much; lead compensation restores phase margin after integrators are added. The system type framework tells you what accuracy is theoretically achievable; compensation tells you how to achieve it while keeping the loop stable.