A processor uses 4 KB pages and has a fully loaded 64-entry TLB. What is the maximum total memory range that could be covered without a TLB miss?
A64 bytes — each TLB entry covers one byte
B64 KB — one byte per entry times 1,024 entries
C256 KB — 64 entries × 4 KB per page
D4 MB — each TLB entry caches an entire 4 MB segment
Each TLB entry maps one virtual page number to one physical page number, and each page is 4 KB. With 64 entries fully populated, the TLB can cover 64 × 4 KB = 256 KB of address space without any misses. This illustrates why even a small TLB achieves high hit rates — programs tend to use a working set of a few dozen pages repeatedly (locality of reference), and those pages fit comfortably in a 64-entry TLB. Options A and B confuse entry count with bytes. Option D describes large page support, not standard 4 KB pages.
Question 2 Multiple Choice
On a MIPS processor (software-managed TLB), what happens when the CPU encounters a TLB miss?
AThe processor halts until the user program re-issues the memory access
BThe hardware automatically walks the page table and fills the TLB entry
CA TLB miss exception is raised, and the OS trap handler looks up the translation and loads it into the TLB
DThe memory access is aborted and the process is killed with a segmentation fault
MIPS uses a software-managed TLB: on a miss, the CPU raises an exception (TLB miss trap), transferring control to the OS's trap handler. The OS finds the correct translation in the page table and writes it into the TLB, then resumes execution. Option B describes the x86 hardware-managed TLB approach — the processor itself walks the page table. Software management costs more per miss but gives the OS flexibility to use any page table format. Options A and D are wrong — a TLB miss is a normal event handled transparently.
Question 3 True / False
Because the TLB is fully associative, each virtual page number typically maps to the same fixed TLB slot, just like a direct-mapped cache.
TTrue
FFalse
Answer: False
Fully associative means the opposite: any virtual page number can be stored in any TLB slot. The TLB searches all entries simultaneously using parallel comparators to find a match — this is what makes it associative. Direct-mapped caches use modulo indexing to send each address to a fixed slot. Full associativity maximizes hit rates (no conflict misses) at the cost of more complex hardware. This is the same associativity trade-off from your cache design studies, applied here to address translation.
Question 4 True / False
TLB entries typically include protection bits that specify read, write, and execute permissions for the corresponding page.
TTrue
FFalse
Answer: True
A TLB entry stores more than just the virtual-to-physical mapping. It includes protection bits (R/W/X permissions), a valid bit, and often an Address Space Identifier (ASID) to distinguish between processes. On a memory access, the processor checks the protection bits in the TLB entry against the type of access — if a user process tries to write to a read-only page, the protection check fails and a fault is raised, even though the translation itself was a TLB hit. This makes the TLB the primary enforcement point for memory protection in most architectures.
Question 5 Short Answer
Why is the TLB necessary given that modern processors already have L1, L2, and L3 caches for fast data access?
Think about your answer, then reveal below.
Model answer: Data caches speed up access to data and instructions, but they operate on physical addresses. Before any cache lookup can happen, the virtual address must be translated to a physical address — and that translation requires a page table lookup, which itself involves multiple memory accesses. Without the TLB, every memory access (including cache hits) would first require several slow memory accesses to traverse the page table. The TLB caches these translations so that address translation costs one cycle instead of tens to hundreds, making the rest of the memory hierarchy viable.
The TLB solves the meta-problem of address translation itself being slow. L1/L2/L3 caches reduce the latency of accessing data once you know its physical address. The TLB reduces the latency of computing that physical address in the first place. The two work together: a typical memory access hits the TLB (fast translation) and then hits L1 cache (fast data access), completing in a handful of cycles. Without the TLB, every access — even L1 cache hits — would first pay a page-table-walk penalty.