Questions: Voltage Divider Principle and Applications

Question 1

A voltage divider has R₁ = 3 kΩ and R₂ = 1 kΩ with V_in = 12 V. A 1 kΩ load is connected in parallel with R₂. What is the actual V_out?

• A. 3 V — the divider formula gives R₂/(R₁+R₂) × 12 = 3 V regardless of load
• B. 6 V — connecting a load doubles the output due to added current
• C. Approximately 1.7 V — the effective bottom resistance is R₂‖R_L = 500 Ω, giving 500/3500 × 12
• D. 12 V — the load draws current that raises the output to the supply voltage

Answer: (C)

With a 1 kΩ load in parallel with R₂ = 1 kΩ, the effective bottom resistance is R₂‖R_L = (1000×1000)/(1000+1000) = 500 Ω. The loaded output is V_out = 12 × 500/(3000+500) ≈ 1.71 V. Option A uses the unloaded formula and gets 3 V — correct only when no load is connected. The loading effect here is severe because R_L equals R₂, halving the effective bottom resistance and dramatically reducing V_out.

Question 2

In a voltage divider with R₁ = 100 Ω and R₂ = 900 Ω and V_in = 10 V, what is the unloaded V_out?

• A. 1 V — using R₁/(R₁+R₂) × V_in
• B. 9 V — using R₂/(R₁+R₂) × V_in
• C. 5 V — resistors always split voltage equally
• D. 10 V — all voltage appears across the larger resistor

Answer: (B)

V_out = V_in × R₂/(R₁+R₂) = 10 × 900/1000 = 9 V. The output is measured across R₂ (the bottom resistor), so it takes the fraction R₂/(R₁+R₂) of the input. Option A uses R₁ in the numerator — a common error from confusing which resistor is on top versus on bottom. Option C assumes equal splitting, which only occurs when R₁ = R₂.

Question 3

If R₂ is much larger than R₁ in a voltage divider, the output voltage approaches the input voltage.

• T. True
• F. False

Answer: True

When R₂ >> R₁, the ratio R₂/(R₁+R₂) approaches R₂/R₂ = 1, so V_out approaches V_in. Intuitively, almost all the resistance is in the bottom portion of the divider, so almost all the voltage appears across R₂. The other limiting case: when R₂ << R₁, V_out approaches 0. The formula's ratio structure makes both limits immediately readable.

Question 4

Connecting a load resistance in parallel with R₂ raises V_out above the unloaded value.

• T. True
• F. False

Answer: False

Connecting a load in parallel with R₂ always decreases V_out. The parallel combination of R₂ and R_L is always less than R₂ alone (parallel resistors always yield a combined resistance less than either individually). A smaller effective R₂ produces a smaller ratio R_eff/(R₁+R_eff) and therefore a smaller V_out. V_out can only decrease (or stay the same if R_L → ∞) when a load is added — never increase.

Question 5

Why does connecting a load to a voltage divider change its output voltage, and how can a designer mitigate this?

Model answer: The voltage divider formula assumes no current flows out of the output node. A real load draws current, creating a parallel path with R₂ that reduces the effective bottom resistance and pulls V_out below the predicted value. The effect worsens as R_L decreases relative to R₂. Designers mitigate it by: (1) making R₁ and R₂ much smaller than R_L so the load has little relative effect, or (2) inserting a buffer amplifier between the divider and the load — the buffer presents near-infinite input impedance to the divider and isolates the two stages entirely.

The buffer solution is often preferred in precision circuits because making R₁ and R₂ very small wastes power through high quiescent current. A unity-gain op-amp buffer draws essentially no current from the divider, preserving V_out while driving any load impedance. This illustrates a general circuit design principle: use buffering to decouple stages that would otherwise interact through loading effects.