Questions: Binary Counters: Design and Analysis

Question 1

In a 4-bit asynchronous (ripple) counter, how does the most significant bit (bit 3) change relative to the clock edge?

• A. Simultaneously with bit 0, because all flip-flops share the same clock input
• B. After three flip-flop propagation delays, because bit 3 is triggered by bit 2, which is triggered by bit 1, which is triggered by bit 0
• C. After one clock period, because the ripple reaches bit 3 within one cycle
• D. Immediately, but only when carrying from 0111 to 1000

Answer: (B)

In a ripple counter, each flip-flop's output serves as the clock for the next. Bit 0 changes after one flip-flop delay from the clock edge. Bit 1 changes only after bit 0 has settled (another flip-flop delay). Bit 2 waits for bit 1, and bit 3 waits for bit 2. The cumulative delay for bit 3 is 3 flip-flop delays. During this settling time, the counter passes through transient intermediate states — glitches — which can corrupt any downstream logic sampling the counter output.

Question 2

In a synchronous counter, which of the following correctly describes the condition for bit n to toggle on a clock edge?

• A. Bit n toggles every other clock cycle, alternating with bit n−1
• B. Bit n toggles when bit n−1 is currently 1
• C. Bit n toggles when all bits 0 through n−1 are currently 1, implemented by an AND gate across those bits
• D. Bit n toggles when the carry-out of bit n−1's flip-flop is asserted

Answer: (C)

In binary counting, bit n changes when all lower-order bits carry — that is, when bits 0 through n−1 are all 1 simultaneously, because that is the condition right before a carry propagates into position n. This is implemented as an AND gate: if bits 0, 1, …, n−1 are all 1, toggle bit n. All flip-flops receive the same clock and update simultaneously. Option B is too weak — bit n=2 should toggle when bits 0 AND 1 are both 1, not just bit 1 alone.

Question 3

An asynchronous (ripple) counter has no glitch states because most flip-flops are clocked simultaneously from the same system clock.

• T. True
• F. False

Answer: False

This describes a *synchronous* counter, not an asynchronous one. In an asynchronous ripple counter, each flip-flop is clocked by the output of the previous one, creating a chain of sequential triggering. Because each bit settles after the previous one, the counter passes through transient intermediate values between a clock edge and the final stable output. These transient states are glitches. Simultaneous clocking is the defining feature of synchronous counters, which eliminates glitches.

Question 4

In a synchronous counter, the maximum propagation delay before the output is valid is approximately one flip-flop delay plus one AND-gate delay, regardless of the counter's bit width.

• T. True
• F. False

Answer: True

In a synchronous counter, all flip-flops are clocked at the same time. The combinational AND gate for bit n must compute its result before the clock edge, and that computation can be done in parallel for all bits during the preceding clock period. After the clock edge, all flip-flops update simultaneously, and the output is valid after one flip-flop propagation delay. In practice, the AND gate for higher bits is wider (more inputs), adding a small additional gate delay, but this does not grow as a chain the way ripple delay does in asynchronous counters.

Question 5

Explain why asynchronous (ripple) counters produce transient glitch states, and how the synchronous counter design eliminates them.

Model answer: In a ripple counter, each flip-flop is triggered by the output of the flip-flop below it in the chain. When the counter increments, bit 0 changes first, which then triggers bit 1 (after one flip-flop delay), which triggers bit 2, and so on. During the settling period, the counter output cycles through intermediate values — for example, when counting from 0111 to 1000, it briefly passes through 0110, 0100, 0000 before reaching 1000. Any circuit reading the counter during these transient states sees incorrect values. A synchronous counter eliminates this by clocking all flip-flops from the same signal and using combinational AND logic to pre-compute which bits toggle — all flip-flops update simultaneously on the clock edge, and the output is valid (after one flip-flop + one AND delay) with no intermediate glitch states.

The fundamental trade-off is simplicity vs. reliability. Ripple counters are simple to chain (just connect Q to CLK of the next flip-flop), but the ripple delay accumulates with bit width and produces glitches. Synchronous counters require extra AND logic per stage but guarantee clean, simultaneous outputs — essential for reliable operation in larger digital systems.