Binary counters increment (or decrement) on each clock pulse. Asynchronous counters use flip-flop output rippling as a carry chain; synchronous counters use combinational logic to set all bits simultaneously, avoiding propagation delays.
A binary counter is one of the most fundamental sequential circuits, and it builds directly on the D flip-flop you already understand. At its core, a counter is just a register that adds 1 to its own value on every clock edge. The simplest way to see why flip-flops naturally count is to consider a single toggle flip-flop (T flip-flop): it flips its output on every clock pulse, producing a pattern 0, 1, 0, 1 — that is the least significant bit of a binary count.
An asynchronous (ripple) counter chains T flip-flops together, with each flip-flop's output serving as the clock input for the next. The first flip-flop toggles on every system clock pulse (bit 0). The second flip-flop toggles only when bit 0 transitions from 1 to 0 — which is exactly when a binary carry propagates. The third toggles when bit 1 falls, and so on. The result is a binary counting sequence: 000, 001, 010, 011, 100, and so on. The design is beautifully simple — just chain flip-flops — but it has a critical flaw: each bit changes only after the previous bit has settled, creating a ripple delay that accumulates. For a 4-bit counter, the most significant bit changes three flip-flop delays after the clock edge. During that settling time, the output passes through transient "glitch" states, which can cause problems if other circuits sample the counter mid-transition.
A synchronous counter fixes this by clocking all flip-flops from the same system clock. Instead of letting each flip-flop trigger the next, combinational logic determines *which* flip-flops should toggle on each clock edge. Bit 0 always toggles (it changes every cycle). Bit 1 toggles when bit 0 is 1 (a carry from position 0). Bit 2 toggles when both bits 0 and 1 are 1 (a carry rippled through two positions). The general rule: bit *n* toggles when all lower bits are 1, which is computed by an AND gate across bits 0 through n−1. Because all flip-flops update simultaneously on the same clock edge, there are no glitch states, and the counter output is valid immediately after one flip-flop propagation delay plus one AND-gate delay.
Counters appear everywhere in digital systems. A program counter in a CPU is a counter that increments to the next instruction address (with additional logic for branches and jumps). Timer circuits, frequency dividers, memory address generators, and state machine sequencers all rely on counters. Variations include up/down counters (a control signal selects increment or decrement), modulo-N counters (reset to zero after reaching N−1, useful for dividing a clock frequency by N), and loadable counters (which can be preset to an arbitrary value). Understanding the synchronous counter's AND-gate carry chain also previews the carry-lookahead concept you will encounter in fast adder circuits — both solve the same fundamental problem of making a rippling dependency resolve in parallel.