Questions: Memory Organization and Addressing

Question 1

A processor has a 24-bit address bus. What is the maximum amount of byte-addressable memory it can directly access?

• A. 24 bytes
• B. 2^16 = 65,536 bytes (64 KB)
• C. 2^24 = 16,777,216 bytes (16 MB)
• D. 2^32 = 4,294,967,296 bytes (4 GB)

Answer: (C)

Each unique address on a 24-bit bus is a 24-bit binary number. The number of distinct addresses is 2^24 = 16,777,216. Since the system is byte-addressable, each address refers to one byte, so the maximum addressable memory is 16 MB. This is a direct consequence of the binary number system: n address bits → 2^n distinct locations.

Question 2

In a little-endian system, the most significant byte of a multi-byte integer is stored at the lowest memory address.

• T. True
• F. False

Answer: False

Little-endian stores the least significant byte (the 'little end') at the lowest address. For example, the 32-bit value 0x12345678 stored at address 0x100 would place 0x78 at 0x100, 0x56 at 0x101, 0x34 at 0x102, and 0x12 at 0x103. Big-endian does the opposite: 0x12 at 0x100. This distinction matters when reading binary files, interpreting network packet headers, or debugging memory dumps — a common source of bugs when exchanging data between x86 (little-endian) and network-standard (big-endian) byte order.

Question 3

Memory is described as byte-addressable, meaning every individual byte has a unique address. Does this mean a processor accesses exactly one byte per memory operation? Explain why or why not.

Model answer: No. 'Byte-addressable' means the addressing granularity is one byte — each byte has a distinct address — but processors almost always read and write full words (4 or 8 bytes) per memory cycle for efficiency. Accessing a single byte typically requires loading the entire aligned word containing it, modifying the target byte, and writing the word back. Many architectures require or strongly prefer word-aligned accesses; an unaligned access (a word that spans two aligned boundaries) may require two memory bus cycles or trigger a hardware exception.

The byte-addressable model is an abstraction for the programmer's view of memory. The physical memory system is optimized for word-width transfers matching the data bus width. Understanding this gap matters for writing efficient C code (struct padding, alignment attributes), for debugging memory errors with tools like valgrind, and for understanding why cache lines transfer 64 bytes at once even when you read a single variable.