Questions: Performance Metrics, Power, and Thermal Management

Question 1

Processor A runs at 4 GHz with an IPC of 1. Processor B runs at 2 GHz with an IPC of 3. Which processor executes more instructions per second?

• A. Processor A — it has a higher clock speed
• B. Processor B — 2 GHz × 3 IPC = 6 billion instructions per second versus 4 billion for A
• C. They are equal — clock speed and IPC cancel out
• D. Cannot be determined without knowing the workload

Answer: (B)

Instructions per second = clock frequency × IPC. Processor A delivers 4 × 1 = 4 billion instructions/second; Processor B delivers 2 × 3 = 6 billion. This is the core reason raw clock speed comparisons between different architectures are misleading — a slower-clocked chip with higher IPC can outperform a faster-clocked one. Option A is the classic misconception: equating clock speed with performance.

Question 2

A chip designer reduces supply voltage from 1.0V to 0.5V while keeping frequency constant. By approximately how much does dynamic power decrease?

• A. 25% — power drops proportionally to voltage
• B. 50% — power drops proportionally to the voltage reduction
• C. 75% — power scales with V², so halving voltage cuts power to one-quarter
• D. 87.5% — power scales with V³ in CMOS

Answer: (C)

Dynamic power follows P = α × C × V² × f. The voltage term is squared, so when V is halved from 1.0 to 0.5, V² drops from 1.0 to 0.25 — a 75% reduction. This non-linear relationship is why voltage scaling has been the most powerful lever for power reduction in processor design, and why the inability to further reduce voltage (due to leakage currents at nanometer scales) triggered the end of Dennard scaling.

Question 3

Thermal throttling means a chip designed to run at a high frequency may actually operate at a lower frequency in sustained use.

• T. True
• F. False

Answer: True

When chip temperature exceeds safe limits (around 100°C for silicon), the processor must throttle — reducing voltage and frequency to stay within thermal bounds. A chip might theoretically run at 5 GHz but sustain only 3.5 GHz when thermal dissipation capacity is exceeded. TDP (Thermal Design Power) is the key rating: it represents the maximum sustained heat a cooling solution must handle, and designs that exceed it will thermally throttle regardless of rated clock speed.

Question 4

The end of Dennard scaling around 2005 meant that transistors could no longer be made smaller.

• T. True
• F. False

Answer: False

Transistors continued to shrink after 2005 — the end of Dennard scaling was not about physical size. Dennard scaling predicted that as transistors shrank, voltage would drop proportionally, keeping power density constant. What broke down was the voltage reduction: at nanometer scales, leakage currents made further voltage reduction impractical. The result was that smaller transistors no longer came with proportional power savings, causing power density to rise. This forced the industry's pivot to multi-core designs rather than higher clock speeds.

Question 5

Explain why increasing clock frequency beyond a certain point produces diminishing returns for overall system performance, even if the processor can physically sustain the higher frequency.

Model answer: Overall performance depends on instruction count, CPI, and clock period together (execution time = IC × CPI × clock period). Higher frequency reduces the clock period, but if CPI also increases (e.g., because more pipeline stages create longer stalls or memory latency becomes a larger fraction of cycles), the gains cancel out. Additionally, power scales with frequency, and power → heat → throttling can force the chip to reduce frequency anyway. The memory wall further limits gains: if the CPU is frequently waiting for memory, faster computation doesn't help.

This question targets the key insight that clock speed is one of three factors in the performance equation. IPC (or CPI) and instruction count matter equally. Real-world systems are also often memory-bound: if the bottleneck is fetching data from DRAM, running the CPU faster just produces more stalls. Thermal limits compound this — a chip boosted above its sustainable thermal envelope will throttle, erasing the theoretical frequency gain. Architects therefore chase IPC improvements, better cache hierarchies, and power efficiency alongside raw frequency.