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CPU performance is measured by clock speed, IPC (instructions per cycle), and latency. Power consumption is proportional to voltage, frequency, and switching activity; thermal dissipation must be managed via cooling. Trade-offs between performance and power are fundamental to processor design.
Compare performance (cycles per instruction), power (watts), and thermal design power (TDP) across generations; understand Dennard scaling limits.
Higher clock speed does not always mean better performance—IPC matters equally. Power consumption scales superlinearly with voltage; thermal limits often constrain clock speed.
From your work with pipelining and caches, you understand how processors execute instructions efficiently. But there is a question lurking behind every architectural optimization: how do we actually measure whether a design is "better"? The answer requires three interrelated metrics — performance, power, and thermal behavior — and understanding their tradeoffs is what separates textbook architecture from real-world chip design.
Performance starts with a deceptively simple equation: execution time = instruction count x CPI x clock period. Instruction count depends on the ISA and compiler. CPI (cycles per instruction) — or its inverse, IPC (instructions per cycle) — captures how efficiently the microarchitecture executes those instructions. Clock period is determined by the critical path through the pipeline. This is why raw clock speed comparisons between different architectures are misleading. A processor running at 3 GHz with an IPC of 2 completes the same work as one running at 6 GHz with an IPC of 1 — but the slower-clocked chip might use far less power doing it.
Dynamic power — the dominant source of power consumption in CMOS circuits — follows the formula P = alpha x C x V2 x f, where alpha is the switching activity factor, C is capacitance, V is supply voltage, and f is clock frequency. The voltage term is squared, which has profound consequences: reducing voltage by half cuts dynamic power by 75%, not 50%. This is why voltage scaling has historically been the most powerful lever for reducing power. Dennard scaling predicted that as transistors shrank, voltage would drop proportionally, keeping power density constant. This worked beautifully until around 2005, when leakage currents at nanometer scales made further voltage reduction impractical. The end of Dennard scaling is why clock speeds plateaued around 4-5 GHz and the industry pivoted to multi-core designs.
Thermal Design Power (TDP) represents the maximum sustained heat a cooling solution must dissipate. Every watt of power consumed becomes a watt of heat. When chip temperatures exceed safe limits (typically around 100°C for silicon), the processor must throttle — reducing voltage and frequency to stay within thermal bounds. This creates a fundamental ceiling: you can design a chip that would theoretically run at 7 GHz, but if no practical cooling solution can remove the resulting heat, the chip will throttle down to a lower speed in practice. Modern processors use dynamic voltage and frequency scaling (DVFS) to continuously adjust their operating point, boosting clock speed when thermal headroom exists and backing off when the chip runs hot. The art of processor design today is not maximizing any single metric but navigating the three-way tradeoff between performance, power, and thermals.