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A multicore processor places several complete processor cores on one chip, each able to run its own thread, usually sharing a last-level cache and main memory. Chip makers turned to multicore designs in the mid-2000s because raising clock rates further had become limited by power and heat. Hardware multithreading is a related idea inside a single core: the core keeps the state of several threads and switches among them, or issues from several at once, to keep its pipeline busy while one thread waits. Both deliver speed only when software supplies multiple threads of work.
Start from the power problem: show that dynamic power grows with clock frequency and with the square of voltage, so faster single cores ran into heat limits. Use Flynn's taxonomy to place a multicore chip as MIMD. Then sketch one pipeline over time for coarse-grained, fine-grained and simultaneous multithreading, coloring each issue slot by thread, and finish with Amdahl's law calculations to show why serial code limits the gain.
For decades, programs got faster each year without any changes because processor clock rates kept climbing. In the mid-2000s that trend stalled. Dynamic power in a chip grows with clock frequency and with the square of supply voltage. Voltages could no longer be lowered much, so higher clock rates meant chips too hot to cool cheaply. Transistors were still shrinking, though, so designers had more of them to spend. They spent them on more cores.
A multicore processor is several full cores, each with its own pipeline, registers and usually private L1 and L2 caches, on one chip. The cores typically share a last-level cache and the connection to main memory. In Michael Flynn's 1966 taxonomy, which classifies machines by instruction streams and data streams, a multicore chip is MIMD: multiple instruction streams operating on multiple data streams. All cores see one shared address space, so threads communicate by reading and writing memory. Because each core caches data, the chip needs a cache coherence protocol so that a write by one core is seen correctly by the others.
Hardware multithreading attacks a different problem: a single core's pipeline often sits idle, for example while waiting hundreds of cycles for a cache miss. If the core holds the state of several threads, with a separate program counter and register set for each, it can use those idle slots. In coarse-grained multithreading the core switches threads only on long stalls. In fine-grained multithreading it switches every cycle. In simultaneous multithreading (SMT), used in Intel's Hyper-Threading, a superscalar core issues instructions from several threads in the same cycle. The operating system sees each hardware thread as a logical processor.
None of this helps a program that has only one thread. Software must expose parallelism, and Amdahl's law limits the payoff. If a fraction s of the work is serial, the speedup on n cores is at most 1 / (s + (1 - s) / n). With s = 0.1, even unlimited cores cannot exceed 10x. Sharing also brings costs: threads that touch the same data need locks or atomic operations, and cores contending for one memory system can slow one another down.
Multicore and multithreaded designs are now standard in phones, laptops and servers. The next step in the same direction is the GPU, which runs thousands of simple threads at once.