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Cache Replacement Policies

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Cache Memory Design→→Cache Associativity and Address Mapping StrategiesPage Replacement Algorithms+1 more
LRU FIFO replacement-policy cache-eviction

Core Idea

When a cache is full and a new block must be loaded, a replacement policy chooses which existing block to evict. Least Recently Used (LRU) evicts the block not accessed for the longest time, exploiting temporal locality. First-In First-Out (FIFO) evicts the oldest loaded block regardless of access recency. Random replacement evicts a randomly chosen block and is surprisingly competitive in practice. LRU is optimal for many workloads but expensive to implement exactly in large caches; pseudo-LRU approximations are used instead.

How It's Best Learned

Simulate LRU, FIFO, and random replacement on a small cache with a fixed access sequence. Count misses for each policy and compare. Explore Belady's anomaly — FIFO can have more misses with a larger cache — as a counterintuitive result.

Common Misconceptions

Explainer

From your study of cache memory design, you know that a cache holds a small, fast copy of recently accessed data from main memory. But caches are finite — a typical L1 cache might hold only 64 KB while main memory holds gigabytes. When every slot in a cache set is occupied and a new block needs to be loaded, the cache must evict one of the existing blocks to make room. The replacement policy is the rule that decides which block to sacrifice, and it has a direct impact on how often the cache misses.

The most intuitive policy is Least Recently Used (LRU): evict whichever block has gone the longest without being accessed. The reasoning follows from temporal locality — if a block was used recently, it is likely to be used again soon, so evicting the least-recently-used block is the safest bet. For a 2-way set-associative cache, LRU is trivial: a single bit per set records which of the two blocks was accessed more recently. But for 8-way or 16-way associativity, true LRU requires tracking the full access order of all blocks in the set, which demands log2(n!) bits of state and complex update logic. This hardware cost is why real processors use pseudo-LRU approximations — tree-based schemes that track "roughly least recent" with far fewer bits.

FIFO (First-In, First-Out) takes a simpler approach: evict whichever block was *loaded* earliest, regardless of whether it was accessed recently. FIFO is cheaper to implement (just a circular pointer per set) and performs reasonably well, but it has a famous pathology called Belady's anomaly: increasing the cache size can actually *increase* the miss rate for certain access patterns. This counterintuitive result does not occur with LRU, which is one reason LRU is generally preferred despite its higher implementation cost.

Random replacement simply picks a victim at random. It requires almost no bookkeeping — just a pseudo-random number generator shared across the cache. While it sounds crude, random replacement avoids the worst-case access patterns that can degrade LRU and FIFO (such as cyclic scans through a working set slightly larger than the cache, where LRU evicts exactly the block that will be needed next). In practice, random replacement performs within a few percent of LRU for many workloads, which is why architectures like ARM Cortex processors have used it. The choice of replacement policy is ultimately an engineering tradeoff between hit rate, hardware complexity, and robustness to adversarial access patterns.

Practice Questions 5 questions

Prerequisite Chain

Understanding Zero → The Number Zero → Counting to Five → Counting to 10 → Counting to 20 → Counting a Set of Objects Up to 20 → Cardinality: The Last Number Counted → Matching Numerals to Quantities → Subitizing Small Quantities → Addition Within 10 → Number Bonds to 10 → Addition Within 20 → Doubles and Near Doubles → Doubles Facts Within 10 → Near Doubles Facts Within 20 → Mental Math Strategies for Addition → Mental Math: Adding and Subtracting Tens → Addition Within 100 → Repeated Addition as Multiplication → Multiplication as Equal Groups → Multiplication: Arrays → Basic Multiplication Facts (0s, 1s, 2s, 5s, 10s) → Multiplication Facts Within 100 → Division as Equal Sharing → Division as Grouping (Measurement Division) → Division: Grouping (Repeated Subtraction) Model → Division: Fair Sharing Model → Division as Equal Sharing → Division as Grouping → Basic Division Facts → Division Facts Within 100 → Multiplication and Division Fact Families → Relationship Between Multiplication and Division → Division Facts as Inverse of Multiplication → Remainders and Quotients in Division → Division Word Problems → Multi-Step Word Problems → Solving Multi-Step Word Problems → Multiplication Word Problems → Division Word Problems → Introduction to Long Division → Factors and Multiples → Prime and Composite Numbers → Equivalent Fractions → Relating Fractions and Decimals → Decimal Place Value → Integers and the Number Line → Comparing and Ordering Integers → Absolute Value → Adding Integers → Subtracting Integers → Multiplying Integers → Introduction to Exponents → Order of Operations → Integer Order of Operations → Variable Expressions → The Distributive Property → Variables and Expressions Review → Introduction to Polynomials → Adding and Subtracting Polynomials → Multiplying Polynomials → Factorial → Permutations → Combinations → Counting Principles: Addition and Multiplication Rules → Introduction to Graph Theory → Propositional Logic Foundations → Logical Equivalences → Boolean Algebra → Boolean Type and Truth Values → Comparison Operators and Boolean Tests → Logical Operators and Boolean Algebra → Boolean Algebra and Fundamental Laws → Logic Gates Fundamentals → Implementing Boolean Functions with Gates → Karnaugh Map Simplification → Combinational Circuit Design → Flip-Flops and Latches → Binary Counters: Design and Analysis → Binary Arithmetic → Fixed-Point Number Representation → Two's Complement Representation → Overflow and Underflow Detection → Binary Adders: Half-Adders and Full-Adders → Full Adder and Carry Propagation → Carry Lookahead Adder Design → Half Adder Circuit Design → Multiplication Circuit Design → Sequential Circuit Design → Registers and Register Files → Instruction Set Architecture (ISA) → Assembly Language Basics → Memory Organization and Addressing → Memory Hierarchy → Cache Memory Design → Cache Replacement Policies

Longest path: 96 steps · 355 total prerequisite topics

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