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Page Fault Handling and Recovery

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Exception Handling: OS InternalsVirtual Address Translation: Paging and TLBs→→Working Set Model and Thrashing
page-faults virtual-memory handling

Core Idea

A page fault occurs when a process accesses a non-resident page. The handler finds or allocates the page, evicts a victim if needed, performs disk I/O, updates page tables, and resumes. Replacement policy (LRU, FIFO) significantly affects performance.

Explainer

From your study of virtual address translation, you know that each virtual address is mapped to a physical frame through a page table, and that the page table entry contains a valid bit indicating whether the page is currently in physical memory. From your understanding of exception handling in the OS, you know that hardware can trap into the kernel when something goes wrong during instruction execution. A page fault connects these two concepts: when the CPU tries to translate a virtual address and finds the valid bit is clear, it raises a page fault exception, transferring control to the kernel's page fault handler.

The page fault handler must determine why the page is not resident and respond appropriately. Not all page faults are equal. An illegal access — the process is trying to read memory it never allocated — results in a segmentation fault and process termination. But the common case is a valid page fault: the page belongs to the process but has been swapped out to disk or has never been loaded (for example, a page of a memory-mapped file being accessed for the first time). In this case, the handler must bring the page into physical memory so the process can continue.

The handler follows a specific sequence. First, it identifies which virtual page caused the fault and locates the page's data on disk (in the swap area or in a file). Next, it finds a free physical frame. If no free frame is available, the handler must choose a victim page to evict — this is where the page replacement policy comes in. Policies like LRU (Least Recently Used) evict the page that has gone longest without being accessed, betting that past access patterns predict future ones. FIFO evicts the oldest page, which is simpler to implement but can evict frequently used pages. If the victim page has been modified (its dirty bit is set), it must be written back to disk before its frame can be reused; if it is clean, the frame can be reclaimed immediately.

Once a frame is available, the handler initiates a disk read to load the faulted page into the frame. This I/O operation takes milliseconds — an eternity compared to nanosecond memory accesses — so the handler blocks the faulting process and switches to another ready process while the I/O completes. When the disk transfer finishes, the handler updates the page table to point the virtual page at the new frame, sets the valid bit, and marks the faulting process as ready to run. The next time that process is scheduled, the CPU retries the instruction that caused the fault, this time finding a valid mapping and proceeding normally.

The performance of virtual memory depends critically on keeping page faults rare. Each fault costs disk I/O — roughly 10 milliseconds — while a normal memory access takes roughly 100 nanoseconds. A page fault is therefore about 100,000 times slower than a memory hit. Even a fault rate of one in a thousand memory accesses would slow a program dramatically. This is why the choice of replacement policy matters so much: a good policy keeps the process's working set — the pages it is actively using — resident in memory, making faults rare. A poor policy evicts pages that will be needed again soon, causing a cascade of faults known as thrashing that can bring a system to its knees.

Practice Questions 5 questions

Prerequisite Chain

Understanding Zero → The Number Zero → Counting to Five → Counting to 10 → Counting to 20 → Counting a Set of Objects Up to 20 → Cardinality: The Last Number Counted → Matching Numerals to Quantities → Subitizing Small Quantities → Addition Within 10 → Number Bonds to 10 → Addition Within 20 → Doubles and Near Doubles → Doubles Facts Within 10 → Near Doubles Facts Within 20 → Mental Math Strategies for Addition → Mental Math: Adding and Subtracting Tens → Addition Within 100 → Repeated Addition as Multiplication → Multiplication as Equal Groups → Multiplication: Arrays → Basic Multiplication Facts (0s, 1s, 2s, 5s, 10s) → Multiplication Facts Within 100 → Division as Equal Sharing → Division as Grouping (Measurement Division) → Division: Grouping (Repeated Subtraction) Model → Division: Fair Sharing Model → Division as Equal Sharing → Division as Grouping → Basic Division Facts → Division Facts Within 100 → Multiplication and Division Fact Families → Relationship Between Multiplication and Division → Division Facts as Inverse of Multiplication → Remainders and Quotients in Division → Division Word Problems → Multi-Step Word Problems → Solving Multi-Step Word Problems → Multiplication Word Problems → Division Word Problems → Introduction to Long Division → Factors and Multiples → Prime and Composite Numbers → Equivalent Fractions → Relating Fractions and Decimals → Decimal Place Value → Integers and the Number Line → Comparing and Ordering Integers → Absolute Value → Adding Integers → Subtracting Integers → Multiplying Integers → Introduction to Exponents → Order of Operations → Integer Order of Operations → Variable Expressions → The Distributive Property → Variables and Expressions Review → Introduction to Polynomials → Adding and Subtracting Polynomials → Multiplying Polynomials → Factorial → Permutations → Combinations → Counting Principles: Addition and Multiplication Rules → Introduction to Graph Theory → Propositional Logic Foundations → Logical Equivalences → Boolean Algebra → Boolean Type and Truth Values → Comparison Operators and Boolean Tests → Logical Operators and Boolean Algebra → Boolean Algebra and Fundamental Laws → Logic Gates Fundamentals → Implementing Boolean Functions with Gates → Karnaugh Map Simplification → Combinational Circuit Design → Flip-Flops and Latches → Binary Counters: Design and Analysis → Binary Arithmetic → Fixed-Point Number Representation → Two's Complement Representation → Overflow and Underflow Detection → Binary Adders: Half-Adders and Full-Adders → Full Adder and Carry Propagation → Carry Lookahead Adder Design → Half Adder Circuit Design → Multiplication Circuit Design → Sequential Circuit Design → Registers and Register Files → Instruction Set Architecture (ISA) → Assembly Language Basics → Memory Organization and Addressing → Memory Address Decoding → Memory Bus Architecture and Interconnect → I/O Systems and Buses → Interrupts and Direct Memory Access (DMA) → Interrupt Vector Tables and Dispatch → Exception Handling: OS Internals → Page Fault Handling and Recovery

Longest path: 100 steps · 376 total prerequisite topics

Prerequisites (2)

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